Files
wasmtime/cranelift/filetests/regalloc/unreachable_code.cton
Dan Gohman 4e67e08efd Use the target-lexicon crate.
This switches from a custom list of architectures to use the
target-lexicon crate.

 - "set is_64bit=1; isa x86" is replaced with "target x86_64", and
   similar for other architectures, and the `is_64bit` flag is removed
   entirely.

 - The `is_compressed` flag is removed too; it's no longer being used to
   control REX prefixes on x86-64, ARM and Thumb are separate
   architectures in target-lexicon, and we can figure out how to
   select RISC-V compressed encodings when we're ready.
2018-05-30 06:13:35 -07:00

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; Use "test compile" here otherwise the dead blocks won't be eliminated.
test compile
set probestack_enabled=0
target x86_64 haswell
; This function contains unreachable blocks which trip up the register
; allocator if they don't get cleared out.
function %unreachable_blocks(i64 vmctx) -> i32 baldrdash {
ebb0(v0: i64):
v1 = iconst.i32 0
v2 = iconst.i32 0
jump ebb2
ebb2:
jump ebb4
ebb4:
jump ebb2
; Everything below this point is unreachable.
ebb3(v3: i32):
v5 = iadd.i32 v2, v3
jump ebb6
ebb6:
jump ebb6
ebb7(v6: i32):
v7 = iadd.i32 v5, v6
jump ebb8
ebb8:
jump ebb10
ebb10:
jump ebb8
ebb9(v8: i32):
v10 = iadd.i32 v7, v8
jump ebb1(v10)
ebb1(v11: i32):
return v11
}