4e67e08efd
This switches from a custom list of architectures to use the target-lexicon crate. - "set is_64bit=1; isa x86" is replaced with "target x86_64", and similar for other architectures, and the `is_64bit` flag is removed entirely. - The `is_compressed` flag is removed too; it's no longer being used to control REX prefixes on x86-64, ARM and Thumb are separate architectures in target-lexicon, and we can figure out how to select RISC-V compressed encodings when we're ready.
40 lines
924 B
Plaintext
40 lines
924 B
Plaintext
test regalloc
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target i686 haswell
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function %pr165() system_v {
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ebb0:
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v0 = iconst.i32 0x0102_0304
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v1 = iconst.i32 0x1102_0304
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v2 = iconst.i32 0x2102_0304
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v20 = ishl v1, v0
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v21 = ishl v2, v0
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v22 = sshr v1, v0
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v23 = sshr v2, v0
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v24 = ushr v1, v0
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v25 = ushr v2, v0
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istore8 v0, v1+0x2710
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istore8 v1, v0+0x2710
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return
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}
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; Same as above, but use so many registers that spilling is required.
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; Note: This is also a candidate for using xchg instructions.
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function %emergency_spill() system_v {
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ebb0:
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v0 = iconst.i32 0x0102_0304
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v1 = iconst.i32 0x1102_0304
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v2 = iconst.i32 0x2102_0304
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v3 = iconst.i32 0x3102_0304
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v4 = iconst.i32 0x4102_0304
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v20 = ishl v1, v0
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v21 = ishl v2, v3
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v22 = sshr v1, v0
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v23 = sshr v2, v0
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v24 = ushr v1, v0
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v25 = ushr v2, v0
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istore8 v0, v1+0x2710
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istore8 v1, v0+0x2710
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istore8 v3, v4+0x2710
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return
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}
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