4e67e08efd
This switches from a custom list of architectures to use the target-lexicon crate. - "set is_64bit=1; isa x86" is replaced with "target x86_64", and similar for other architectures, and the `is_64bit` flag is removed entirely. - The `is_compressed` flag is removed too; it's no longer being used to control REX prefixes on x86-64, ARM and Thumb are separate architectures in target-lexicon, and we can figure out how to select RISC-V compressed encodings when we're ready.
52 lines
1.6 KiB
Plaintext
52 lines
1.6 KiB
Plaintext
test regalloc
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target x86_64 haswell
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; Test combinations of constraints.
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;
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; The x86 ushr instruction requires its second operand to be passed in %rcx and its output is
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; tied to the first input operand.
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;
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; If we pass the same value to both operands, both constraints must be satisfied.
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; Found by the Binaryen fuzzer in PR221.
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;
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; Conditions triggering the problem:
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;
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; - The same value used for a tied operand and a fixed operand.
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; - The common value is already in %rcx.
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; - The tied output value is live outside the EBB.
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;
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; Under these conditions, Solver::add_tied_input() would create a variable for the tied input
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; without considering the fixed constraint.
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function %pr221(i64 [%rdi], i64 [%rsi], i64 [%rdx], i64 [%rcx]) -> i64 [%rax] {
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ebb0(v0: i64, v1: i64, v2: i64, v3: i64):
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v4 = ushr v3, v3
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jump ebb1
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ebb1:
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return v4
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}
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; Found by the Binaryen fuzzer in PR218.
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;
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; This is a similar situation involving combined constraints on the ushr instruction:
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;
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; - The %rcx register is already in use by a globally live value.
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; - The ushr x, x result is also a globally live value.
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;
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; Since the ushr x, x result is forced to be placed in %rcx, we must set the replace_global_defines
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; flag so it can be reassigned to a different global register.
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function %pr218(i64 [%rdi], i64 [%rsi], i64 [%rdx], i64 [%rcx]) -> i64 [%rax] {
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ebb0(v0: i64, v1: i64, v2: i64, v3: i64):
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; check: regmove v3, %rcx ->
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v4 = ushr v0, v0
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; check: v4 = copy
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jump ebb1
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ebb1:
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; v3 is globally live in %rcx.
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; v4 is also globally live. Needs to be assigned something else for the trip across the CFG edge.
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v5 = iadd v3, v4
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return v5
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}
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