4e67e08efd
This switches from a custom list of architectures to use the target-lexicon crate. - "set is_64bit=1; isa x86" is replaced with "target x86_64", and similar for other architectures, and the `is_64bit` flag is removed entirely. - The `is_compressed` flag is removed too; it's no longer being used to control REX prefixes on x86-64, ARM and Thumb are separate architectures in target-lexicon, and we can figure out how to select RISC-V compressed encodings when we're ready.
38 lines
716 B
Plaintext
38 lines
716 B
Plaintext
test regalloc
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target riscv32
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; Here, the coalescer initially builds vreg0 = [v1, v2, v3]
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;
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; There's interference between v1 and v2 at the brz instruction. Isolating v2 is not going to
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; resolve that conflict since v1 will just interfere with the inserted copy too.
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;function %c1(i32) -> i32 {
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;ebb0(v0: i32):
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; v1 = iadd_imm v0, 1
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; v2 = iconst.i32 1
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; brz v1, ebb1(v2)
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; jump ebb2
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;
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;ebb1(v3: i32):
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; return v3
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;
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;ebb2:
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; jump ebb1(v1)
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;}
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; Same thing with v1 and v2 swapped to reverse the order of definitions.
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function %c2(i32) -> i32 {
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ebb0(v0: i32):
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v1 = iadd_imm v0, 1
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v2 = iconst.i32 1
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brz v2, ebb1(v1)
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jump ebb2
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ebb1(v3: i32):
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return v3
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ebb2:
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jump ebb1(v2)
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}
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