4e67e08efd
This switches from a custom list of architectures to use the target-lexicon crate. - "set is_64bit=1; isa x86" is replaced with "target x86_64", and similar for other architectures, and the `is_64bit` flag is removed entirely. - The `is_compressed` flag is removed too; it's no longer being used to control REX prefixes on x86-64, ARM and Thumb are separate architectures in target-lexicon, and we can figure out how to select RISC-V compressed encodings when we're ready.
28 lines
689 B
Plaintext
28 lines
689 B
Plaintext
test regalloc
|
|
target i686
|
|
|
|
; This test covers the troubles when values with global live ranges are defined
|
|
; by instructions with constrained register classes.
|
|
;
|
|
; The icmp_imm instrutions write their b1 result to the ABCD register class on
|
|
; 32-bit x86. So if we define 5 live values, they can't all fit.
|
|
function %global_constraints(i32) {
|
|
ebb0(v0: i32):
|
|
v1 = icmp_imm eq v0, 1
|
|
v2 = icmp_imm ugt v0, 2
|
|
v3 = icmp_imm sle v0, 3
|
|
v4 = icmp_imm ne v0, 4
|
|
v5 = icmp_imm sge v0, 5
|
|
brnz v5, ebb1
|
|
return
|
|
|
|
ebb1:
|
|
; Make sure v1-v5 are live in.
|
|
v10 = band v1, v2
|
|
v11 = bor v3, v4
|
|
v12 = bor v10, v11
|
|
v13 = bor v12, v5
|
|
trapnz v13, user0
|
|
return
|
|
}
|