4e67e08efd
This switches from a custom list of architectures to use the target-lexicon crate. - "set is_64bit=1; isa x86" is replaced with "target x86_64", and similar for other architectures, and the `is_64bit` flag is removed entirely. - The `is_compressed` flag is removed too; it's no longer being used to control REX prefixes on x86-64, ARM and Thumb are separate architectures in target-lexicon, and we can figure out how to select RISC-V compressed encodings when we're ready.
83 lines
1.8 KiB
Plaintext
83 lines
1.8 KiB
Plaintext
test regalloc
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target i686
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; regex: V=v\d+
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; regex: REG=%r([abcd]x|[sd]i)
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; Tied operands, both are killed at instruction.
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function %tied_easy() -> i32 {
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ebb0:
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v0 = iconst.i32 12
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v1 = iconst.i32 13
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; not: copy
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; check: isub
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v2 = isub v0, v1
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return v2
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}
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; Tied operand is live after instruction.
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function %tied_alive() -> i32 {
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ebb0:
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v0 = iconst.i32 12
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v1 = iconst.i32 13
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; check: $(v0c=$V) = copy v0
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; check: v2 = isub $v0c, v1
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v2 = isub v0, v1
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; check: v3 = iadd v2, v0
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v3 = iadd v2, v0
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return v3
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}
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; Fixed register constraint.
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function %fixed_op() -> i32 {
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ebb0:
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; check: ,%rax]
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; sameln: v0 = iconst.i32 12
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v0 = iconst.i32 12
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v1 = iconst.i32 13
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; The dynamic shift amount must be in %rcx
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; check: regmove v0, %rax -> %rcx
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v2 = ishl v1, v0
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return v2
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}
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; Fixed register constraint twice.
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function %fixed_op_twice() -> i32 {
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ebb0:
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; check: ,%rax]
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; sameln: v0 = iconst.i32 12
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v0 = iconst.i32 12
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v1 = iconst.i32 13
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; The dynamic shift amount must be in %rcx
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; check: regmove v0, %rax -> %rcx
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v2 = ishl v1, v0
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; check: regmove v0, %rcx -> $REG
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; check: regmove v2, $REG -> %rcx
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v3 = ishl v0, v2
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return v3
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}
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; Tied use of a diverted register.
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function %fixed_op_twice() -> i32 {
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ebb0:
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; check: ,%rax]
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; sameln: v0 = iconst.i32 12
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v0 = iconst.i32 12
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v1 = iconst.i32 13
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; The dynamic shift amount must be in %rcx
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; check: regmove v0, %rax -> %rcx
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; check: v2 = ishl v1, v0
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v2 = ishl v1, v0
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; Now v0 is globally allocated to %rax, but diverted to %rcx.
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; Check that the tied def gets the diverted register.
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v3 = isub v0, v2
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; not: regmove
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; check: ,%rcx]
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; sameln: isub
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; Move it into place for the return value.
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; check: regmove v3, %rcx -> %rax
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return v3
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}
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