4e67e08efd
This switches from a custom list of architectures to use the target-lexicon crate. - "set is_64bit=1; isa x86" is replaced with "target x86_64", and similar for other architectures, and the `is_64bit` flag is removed entirely. - The `is_compressed` flag is removed too; it's no longer being used to control REX prefixes on x86-64, ARM and Thumb are separate architectures in target-lexicon, and we can figure out how to select RISC-V compressed encodings when we're ready.
73 lines
1.3 KiB
Plaintext
73 lines
1.3 KiB
Plaintext
test regalloc
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target x86_64 haswell
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; Reported as https://github.com/cretonne/cretonne/issues/216 from the Binaryen fuzzer.
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;
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; The (old) coalescer creates a virtual register with two identical values.
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function %pr216(i32 [%rdi], i64 vmctx [%rsi]) -> i64 [%rax] system_v {
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ebb0(v0: i32, v1: i64):
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v3 = iconst.i64 0
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v5 = iconst.i32 0
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brz v5, ebb3(v3)
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jump ebb4(v3, v3)
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ebb4(v11: i64, v29: i64):
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v6 = iconst.i32 0
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brz v6, ebb14
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v9 = iconst.i32 -17
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v12 = iconst.i32 0xffff_ffff_ffff_8000
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jump ebb9(v12)
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ebb9(v10: i32):
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brnz v10, ebb8(v9, v11, v11)
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brz.i32 v9, ebb13
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v13 = iconst.i32 0
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brnz v13, ebb6(v11, v11)
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v14 = iconst.i32 0
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brz v14, ebb12
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jump ebb11
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ebb12:
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jump ebb4(v11, v11)
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ebb11:
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jump ebb10(v11)
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ebb13:
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v15 = iconst.i64 1
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jump ebb10(v15)
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ebb10(v21: i64):
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v16 = iconst.i32 0
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brnz v16, ebb6(v21, v11)
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v17 = iconst.i32 0xffff_ffff_ffff_9f35
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jump ebb8(v17, v21, v11)
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ebb8(v8: i32, v23: i64, v28: i64):
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jump ebb7(v8, v23, v28)
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ebb14:
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v18 = iconst.i32 0
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jump ebb7(v18, v11, v29)
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ebb7(v7: i32, v22: i64, v27: i64):
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jump ebb6(v22, v27)
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ebb6(v20: i64, v25: i64):
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v19 = iconst.i32 0xffc7
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brnz v19, ebb4(v20, v25)
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jump ebb5
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ebb5:
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jump ebb3(v25)
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ebb3(v24: i64):
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jump ebb2(v24)
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ebb2(v4: i64):
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jump ebb1(v4)
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ebb1(v2: i64):
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return v2
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}
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