f636d795c5
* Start adding the load_complex and store_complex instructions. N.b.: The text format is not correct yet. Requires changes to the lexer and parser. I'm not sure why I needed to change the RuntimeError to Exception yet. Will fix. * Get first few encodings of load_complex working. Still needs var args type checking. * Clean up ModRM helper functions in binemit. * Implement 32-bit displace for load_complex * Use encoding helpers instead of doing them all by hand * Initial implementation of store_complex * Parse value list for load/store_complex with + as delimiter. Looks nice. * Add sign/zero-extension and size variants for load_complex. * Add size variants of store_complex. * Add asm helper lines to load/store complex bin tests. * Example of length-checking the instruction ValueList for an encoding. Extremely questionable implementation. * Fix Python linting issues * First draft of postopt pass to fold adds and loads into load_complex. Just simple loads for now. * Optimization pass now works with all types of loads. * Add store+add -> store_complex to postopt pass * Put complex address optimization behind ISA flag. * Add load/store complex for f32 and f64 * Fixes changes to lexer that broke NaN parsing. Abstracts away the repeated checks for whether or not the characters following a + or - are going to be parsed as a number or not. * Fix formatting issues * Fix register restrictions for complex addresses. * Encoding tests for x86-32. * Add documentation for newly added instructions, recipes, and cdsl changes. * Fix python formatting again * Apply value-list length predicates to all LoadComplex and StoreComplex instructions. * Add predicate types to new encoding helpers for mypy. * Import FieldPredicate to satisfy mypy. * Add and fix some "asm" strings in the encoding tests. * Line-up 'bin' comments in x86/binary64 test * Test parsing of offset-less store_complex instruction. * 'sNaN' not 'sNan' * Bounds check the lookup for polymorphic typevar operand. * Fix encodings for istore16_complex.
242 lines
6.1 KiB
Plaintext
242 lines
6.1 KiB
Plaintext
test cat
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; The smallest possible function.
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function %minimal() {
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ebb0:
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trap user0
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}
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; sameln: function %minimal() fast {
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; nextln: ebb0:
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; nextln: trap user0
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; nextln: }
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; Create and use values.
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; Polymorphic instructions with type suffix.
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function %ivalues() {
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ebb0:
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v0 = iconst.i32 2
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v1 = iconst.i8 6
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v2 = ishl v0, v1
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}
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; sameln: function %ivalues() fast {
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; nextln: ebb0:
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; nextln: v0 = iconst.i32 2
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; nextln: v1 = iconst.i8 6
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; nextln: v2 = ishl v0, v1
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; nextln: }
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; Create and use values.
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; Polymorphic instructions with type suffix.
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function %bvalues() {
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ebb0:
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v0 = bconst.b32 true
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v1 = bconst.b8 false
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v2 = bextend.b32 v1
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v3 = bxor v0, v2
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}
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; sameln: function %bvalues() fast {
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; nextln: ebb0:
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; nextln: v0 = bconst.b32 true
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; nextln: v1 = bconst.b8 false
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; nextln: v2 = bextend.b32 v1
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; nextln: v3 = bxor v0, v2
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; nextln: }
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; Polymorphic instruction controlled by second operand.
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function %select() {
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ebb0(v90: i32, v91: i32, v92: b1):
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v0 = select v92, v90, v91
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}
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; sameln: function %select() fast {
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; nextln: ebb0(v90: i32, v91: i32, v92: b1):
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; nextln: v0 = select v92, v90, v91
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; nextln: }
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; Polymorphic instruction controlled by third operand.
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function %selectif() system_v {
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ebb0(v95: i32, v96: i32, v97: b1):
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v98 = selectif.i32 eq v97, v95, v96
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}
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; sameln: function %selectif() system_v {
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; nextln: ebb0(v95: i32, v96: i32, v97: b1):
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; nextln: v98 = selectif.i32 eq v97, v95, v96
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; nextln: }
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; Lane indexes.
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function %lanes() {
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ebb0:
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v0 = iconst.i32x4 2
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v1 = extractlane v0, 3
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v2 = insertlane v0, 1, v1
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}
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; sameln: function %lanes() fast {
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; nextln: ebb0:
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; nextln: v0 = iconst.i32x4 2
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; nextln: v1 = extractlane v0, 3
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; nextln: v2 = insertlane v0, 1, v1
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; nextln: }
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; Integer condition codes.
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function %icmp(i32, i32) {
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ebb0(v90: i32, v91: i32):
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v0 = icmp eq v90, v91
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v1 = icmp ult v90, v91
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v2 = icmp_imm sge v90, -12
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v3 = irsub_imm v91, 45
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br_icmp eq v90, v91, ebb0(v91, v90)
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}
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; sameln: function %icmp(i32, i32) fast {
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; nextln: ebb0(v90: i32, v91: i32):
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; nextln: v0 = icmp eq v90, v91
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; nextln: v1 = icmp ult v90, v91
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; nextln: v2 = icmp_imm sge v90, -12
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; nextln: v3 = irsub_imm v91, 45
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; nextln: br_icmp eq v90, v91, ebb0(v91, v90)
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; nextln: }
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; Floating condition codes.
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function %fcmp(f32, f32) {
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ebb0(v90: f32, v91: f32):
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v0 = fcmp eq v90, v91
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v1 = fcmp uno v90, v91
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v2 = fcmp lt v90, v91
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}
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; sameln: function %fcmp(f32, f32) fast {
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; nextln: ebb0(v90: f32, v91: f32):
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; nextln: v0 = fcmp eq v90, v91
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; nextln: v1 = fcmp uno v90, v91
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; nextln: v2 = fcmp lt v90, v91
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; nextln: }
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; The bitcast instruction has two type variables: The controlling type variable
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; controls the outout type, and the input type is a free variable.
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function %bitcast(i32, f32) {
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ebb0(v90: i32, v91: f32):
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v0 = bitcast.i8x4 v90
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v1 = bitcast.i32 v91
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}
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; sameln: function %bitcast(i32, f32) fast {
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; nextln: ebb0(v90: i32, v91: f32):
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; nextln: v0 = bitcast.i8x4 v90
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; nextln: v1 = bitcast.i32 v91
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; nextln: }
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; Stack slot references
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function %stack() {
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ss10 = spill_slot 8
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ss2 = explicit_slot 4
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ss3 = incoming_arg 4, offset 8
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ss4 = outgoing_arg 4
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ss5 = emergency_slot 4
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ebb0:
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v1 = stack_load.i32 ss10
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v2 = stack_load.i32 ss10+4
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stack_store v1, ss10+2
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stack_store v2, ss2
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}
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; sameln: function %stack() fast {
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; check: ss2 = explicit_slot 4
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; check: ss3 = incoming_arg 4, offset 8
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; check: ss4 = outgoing_arg 4
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; check: ss5 = emergency_slot 4
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; check: ss10 = spill_slot 8
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; check: ebb0:
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; nextln: v1 = stack_load.i32 ss10
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; nextln: v2 = stack_load.i32 ss10+4
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; nextln: stack_store v1, ss10+2
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; nextln: stack_store v2, ss2
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; Memory access instructions.
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function %memory(i32) {
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ebb0(v1: i32):
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v2 = load.i64 v1
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v3 = load.i64 aligned v1
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v4 = load.i64 notrap v1
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v5 = load.i64 notrap aligned v1
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v6 = load.i64 aligned notrap v1
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v7 = load.i64 v1-12
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v8 = load.i64 notrap v1+0x1_0000
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v9 = load_complex.i64 v1+v2
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v10 = load_complex.i64 v1+v2+0x1
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store v2, v1
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store aligned v3, v1+12
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store notrap aligned v3, v1-12
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store_complex v3, v1+v2
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store_complex v3, v1+v2+0x1
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}
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; sameln: function %memory(i32) fast {
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; nextln: ebb0(v1: i32):
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; nextln: v2 = load.i64 v1
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; nextln: v3 = load.i64 aligned v1
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; nextln: v4 = load.i64 notrap v1
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; nextln: v5 = load.i64 notrap aligned v1
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; nextln: v6 = load.i64 notrap aligned v1
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; nextln: v7 = load.i64 v1-12
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; nextln: v8 = load.i64 notrap v1+0x0001_0000
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; nextln: v9 = load_complex.i64 v1+v2
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; nextln: v10 = load_complex.i64 v1+v2+1
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; nextln: store v2, v1
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; nextln: store aligned v3, v1+12
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; nextln: store notrap aligned v3, v1-12
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; nextln: store_complex v3, v1+v2
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; nextln: store_complex v3, v1+v2+1
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; Register diversions.
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; This test file has no ISA, so we can unly use register unit numbers.
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function %diversion(i32) {
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ss0 = spill_slot 4
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ebb0(v1: i32):
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regmove v1, %10 -> %20
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regmove v1, %20 -> %10
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regspill v1, %10 -> ss0
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regfill v1, ss0 -> %10
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return
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}
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; sameln: function %diversion(i32) fast {
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; nextln: ss0 = spill_slot 4
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; check: ebb0(v1: i32):
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; nextln: regmove v1, %10 -> %20
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; nextln: regmove v1, %20 -> %10
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; nextln: regspill v1, %10 -> ss0
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; nextln: regfill v1, ss0 -> %10
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; nextln: return
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; nextln: }
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; Register copies.
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function %copy_special() {
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ebb0:
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copy_special %10 -> %20
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copy_special %20 -> %10
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return
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}
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; sameln: function %copy_special() fast {
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; nextln: ebb0:
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; nextln: copy_special %10 -> %20
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; nextln: copy_special %20 -> %10
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; nextln: return
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; nextln: }
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function %cond_traps(i32) {
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ebb0(v0: i32):
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trapz v0, stk_ovf
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v1 = ifcmp_imm v0, 5
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trapif ugt v1, oob
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v2 = bitcast.f32 v1
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v3 = ffcmp v2, v2
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trapff uno v3, int_ovf
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return
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}
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; sameln: function %cond_traps(i32)
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; nextln: ebb0(v0: i32):
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; nextln: trapz v0, stk_ovf
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; nextln: v1 = ifcmp_imm v0, 5
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; nextln: trapif ugt v1, oob
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; nextln: v2 = bitcast.f32 v1
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; nextln: v3 = ffcmp v2, v2
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; nextln: trapff uno v3, int_ovf
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; nextln: return
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; nextln: }
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