6606b88136
* Add a pre-opt optimization to change constants into immediates. This converts 'iadd' + 'iconst' into 'iadd_imm', and so on. * Optimize away redundant `bint` instructions. Cretonne has a concept of "Testable" values, which can be either boolean or integer. When the an instruction needing a "Testable" value receives the result of a `bint`, converting boolean to integer, eliminate the `bint`, as it's redundant. * Postopt: Optimize using CPU flags. This introduces a post-legalization optimization pass which converts compare+branch sequences to use flags values on CPUs which support it. * Define a form of x86's `urm` that doesn't clobber FLAGS. movzbl/movsbl/etc. don't clobber FLAGS; define a form of the `urm` recipe that represents this. * Implement a DCE pass. This pass deletes instructions with no side effects and no results that are used. * Clarify ambiguity about "32-bit" and "64-bit" in comments. * Add x86 encodings for icmp_imm. * Add a testcase for postopt CPU flags optimization. This covers the basic functionality of transforming compare+branch sequences to use CPU flags. * Pattern-match irsub_imm in preopt.
47 lines
894 B
Plaintext
47 lines
894 B
Plaintext
test dce
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function %simple() -> i32 {
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ebb0:
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v2 = iconst.i32 2
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v3 = iconst.i32 3
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return v3
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}
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; sameln: function %simple
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; nextln: ebb0:
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; nextln: v3 = iconst.i32 3
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; nextln: return v3
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; nextln: }
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function %some_branching(i32, i32) -> i32 {
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ebb0(v0: i32, v1: i32):
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v3 = iconst.i32 70
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v4 = iconst.i32 71
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v5 = iconst.i32 72
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v8 = iconst.i32 73
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brz v0, ebb1
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jump ebb2(v8)
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ebb1:
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v2 = iadd v0, v3
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return v0
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ebb2(v9: i32):
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v6 = iadd v1, v4
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v7 = iadd v6, v9
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return v7
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}
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; sameln: function %some_branching
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; nextln: ebb0(v0: i32, v1: i32):
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; nextln: v4 = iconst.i32 71
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; nextln: v8 = iconst.i32 73
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; nextln: brz v0, ebb1
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; nextln: jump ebb2(v8)
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; nextln:
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; nextln: ebb1:
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; nextln: return v0
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; nextln:
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; nextln: ebb2(v9: i32):
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; nextln: v6 = iadd.i32 v1, v4
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; nextln: v7 = iadd v6, v9
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; nextln: return v7
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