Dan Gohman 970045c309 Set clobbers_flags to False for urm_noflags_abcd. ...

`urm_noflags` is a variant of `urm` which doesn't clobber the flags, and
`urm_noflags_abcd` is a further variant for ABCD registers, so it also
doesn't clobber the flags.

2018-06-05 11:30:35 -07:00

..

.gitignore

Initial Sphinx configuration.

2016-01-12 16:51:35 -08:00

callex.cton

Update examples to reflect that Cretonne indices typically start at 0.

2018-04-27 06:02:59 -07:00

compare-llvm.rst

Rename intel to x86.

2018-04-12 10:02:16 -07:00

conf.py

Require at least Sphinx 1.4 since the format of index tuples changed.

2018-04-27 06:02:59 -07:00

cton_domain.py

Update examples to reflect that Cretonne indices typically start at 0.

2018-04-27 06:02:59 -07:00

cton_lexer.py

Add heap_addr custom legalization.

2017-08-24 14:44:47 -07:00

example.c

Update language reference.

2016-01-21 14:25:16 -08:00

example.cton

Update examples to reflect that Cretonne indices typically start at 0.

2018-04-27 06:02:59 -07:00

heapex-dyn.cton

Refactor calling convention settings. (#304)

2018-04-22 21:35:18 -07:00

heapex-sm32.cton

Refactor calling convention settings. (#304)

2018-04-22 21:35:18 -07:00

heapex-sm64.cton

Refactor calling convention settings. (#304)

2018-04-22 21:35:18 -07:00

index.rst

Add crate descriptions for cretonne-{module, faerie, simplejit}.

2018-04-17 23:19:10 -07:00

langref.rst

load_complex and store_complex instructions (#309)

2018-05-09 14:07:00 -05:00

make.bat

Use https rather than http for several URLs.

2018-03-05 06:55:27 -08:00

Makefile

Rename the 'cretonne' crate to 'cretonne-codegen'.

2018-04-17 09:46:56 -07:00

metaref.rst

Rename the 'cretonne' crate to 'cretonne-codegen'.

2018-04-17 09:46:56 -07:00

regalloc.rst

Rename intel to x86.

2018-04-12 10:02:16 -07:00

testing.rst

Set clobbers_flags to False for urm_noflags_abcd.

2018-06-05 11:30:35 -07:00