83c3bc5b9d
Implemented the following Opcodes for the Cranelift interpreter: - `Unarrow` to combine two SIMD vectors into a new vector with twice the lanes but half the width, with signed inputs which are clamped to `0x00`. - `Uunarrow` to perform the same operation as `Unarrow` but treating inputs as unsigned. - `Snarrow` to perform the same operation as `Unarrow` but treating both inputs and outputs as signed, and saturating accordingly. Note that all 3 instructions saturate at the type boundaries. Copyright (c) 2021, Arm Limited
20 lines
579 B
Plaintext
20 lines
579 B
Plaintext
test interpret
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test run
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target aarch64
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set enable_simd
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target x86_64
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function %snarrow_i16x8(i16x8, i16x8) -> i8x16 {
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block0(v0: i16x8, v1: i16x8):
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v2 = snarrow v0, v1
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return v2
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}
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; run: %snarrow_i16x8([1 127 128 15 32767 -32 48 0], [8 255 -100 100 -32768 73 80 42]) == [1 127 127 15 127 -32 48 0 8 127 -100 100 -128 73 80 42]
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function %snarrow_i32x4(i32x4, i32x4) -> i16x8 {
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block0(v0: i32x4, v1: i32x4):
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v2 = snarrow v0, v1
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return v2
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}
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; run: %snarrow_i32x4([32767 1048575 -70000 -5], [268435455 73 268435455 42]) == [32767 32767 -32768 -5 32767 73 32767 42]
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