5c1b468648
* x64: Add precise-output tests for div traps
This adds a suite of `*.clif` files which are intended to test the
`avoid_div_traps=true` compilation of the `{s,u}{div,rem}` instructions.
* x64: Remove conditional regalloc in `Div` instruction
Move the 8-bit `Div` logic into a dedicated `Div8` instruction to avoid
having conditionally-used registers with respect to regalloc.
* x64: Migrate non-trapping, `udiv`/`urem` to ISLE
* x64: Port checked `udiv` to ISLE
* x64: Migrate urem entirely to ISLE
* x64: Use `test` instead of `cmp` to compare-to-zero
* x64: Port `sdiv` lowering to ISLE
* x64: Port `srem` lowering to ISLE
* Tidy up regalloc behavior and fix tests
* Update docs and winch
* Review comments
* Reword again
* More refactoring test fixes
* More test fixes
118 lines
2.0 KiB
Plaintext
118 lines
2.0 KiB
Plaintext
test compile precise-output
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target x86_64
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function %f1(i8, i8) -> i8 {
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block0(v0: i8, v1: i8):
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v2 = udiv v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movzbl %dil, %eax
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; div %al, %sil, %al
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movzbl %dil, %eax
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; divb %sil ; trap: int_divz
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f2(i16, i16) -> i16 {
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block0(v0: i16, v1: i16):
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v2 = udiv v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movq %rdi, %rax
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; xorq %rdx, %rdx, %rdx
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; div %ax, %dx, %si, %ax, %dx
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movq %rdi, %rax
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; xorq %rdx, %rdx
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; divw %si ; trap: int_divz
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f3(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = udiv v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movq %rdi, %rax
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; xorq %rdx, %rdx, %rdx
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; div %eax, %edx, %esi, %eax, %edx
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movq %rdi, %rax
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; xorq %rdx, %rdx
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; divl %esi ; trap: int_divz
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f4(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = udiv v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movq %rdi, %rax
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; xorq %rdx, %rdx, %rdx
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; div %rax, %rdx, %rsi, %rax, %rdx
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movq %rdi, %rax
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; xorq %rdx, %rdx
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; divq %rsi ; trap: int_divz
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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