* x64: Add precise-output tests for div traps
This adds a suite of `*.clif` files which are intended to test the
`avoid_div_traps=true` compilation of the `{s,u}{div,rem}` instructions.
* x64: Remove conditional regalloc in `Div` instruction
Move the 8-bit `Div` logic into a dedicated `Div8` instruction to avoid
having conditionally-used registers with respect to regalloc.
* x64: Migrate non-trapping, `udiv`/`urem` to ISLE
* x64: Port checked `udiv` to ISLE
* x64: Migrate urem entirely to ISLE
* x64: Use `test` instead of `cmp` to compare-to-zero
* x64: Port `sdiv` lowering to ISLE
* x64: Port `srem` lowering to ISLE
* Tidy up regalloc behavior and fix tests
* Update docs and winch
* Review comments
* Reword again
* More refactoring test fixes
* More test fixes
855 lines
28 KiB
Rust
855 lines
28 KiB
Rust
use crate::ir::{BlockCall, Value, ValueList};
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use alloc::boxed::Box;
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use alloc::vec::Vec;
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use smallvec::SmallVec;
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use std::cell::Cell;
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pub use super::MachLabel;
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use super::RetPair;
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pub use crate::ir::{
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condcodes, condcodes::CondCode, dynamic_to_fixed, ArgumentExtension, ArgumentPurpose, Constant,
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DynamicStackSlot, ExternalName, FuncRef, GlobalValue, Immediate, SigRef, StackSlot,
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};
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pub use crate::isa::unwind::UnwindInst;
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pub use crate::isa::TargetIsa;
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pub use crate::machinst::{
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ABIArg, ABIArgSlot, InputSourceInst, Lower, LowerBackend, RealReg, Reg, RelocDistance, Sig,
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VCodeInst, Writable,
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};
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pub use crate::settings::{OptLevel, TlsModel};
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pub type Unit = ();
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pub type ValueSlice = (ValueList, usize);
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pub type ValueArray2 = [Value; 2];
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pub type ValueArray3 = [Value; 3];
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pub type BlockArray2 = [BlockCall; 2];
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pub type WritableReg = Writable<Reg>;
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pub type VecRetPair = Vec<RetPair>;
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pub type VecMask = Vec<u8>;
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pub type ValueRegs = crate::machinst::ValueRegs<Reg>;
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pub type WritableValueRegs = crate::machinst::ValueRegs<WritableReg>;
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pub type InstOutput = SmallVec<[ValueRegs; 2]>;
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pub type InstOutputBuilder = Cell<InstOutput>;
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pub type BoxExternalName = Box<ExternalName>;
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pub type Range = (usize, usize);
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pub enum RangeView {
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Empty,
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NonEmpty { index: usize, rest: Range },
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}
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/// Helper macro to define methods in `prelude.isle` within `impl Context for
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/// ...` for each backend. These methods are shared amongst all backends.
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#[macro_export]
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#[doc(hidden)]
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macro_rules! isle_lower_prelude_methods {
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() => {
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isle_common_prelude_methods!();
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#[inline]
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fn value_type(&mut self, val: Value) -> Type {
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self.lower_ctx.dfg().value_type(val)
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}
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#[inline]
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fn value_reg(&mut self, reg: Reg) -> ValueRegs {
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ValueRegs::one(reg)
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}
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#[inline]
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fn value_regs(&mut self, r1: Reg, r2: Reg) -> ValueRegs {
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ValueRegs::two(r1, r2)
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}
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#[inline]
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fn value_regs_invalid(&mut self) -> ValueRegs {
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ValueRegs::invalid()
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}
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#[inline]
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fn output_none(&mut self) -> InstOutput {
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smallvec::smallvec![]
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}
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#[inline]
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fn output(&mut self, regs: ValueRegs) -> InstOutput {
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smallvec::smallvec![regs]
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}
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#[inline]
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fn output_pair(&mut self, r1: ValueRegs, r2: ValueRegs) -> InstOutput {
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smallvec::smallvec![r1, r2]
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}
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#[inline]
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fn output_builder_new(&mut self) -> InstOutputBuilder {
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std::cell::Cell::new(InstOutput::new())
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}
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#[inline]
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fn output_builder_push(&mut self, builder: &InstOutputBuilder, regs: ValueRegs) -> Unit {
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let mut vec = builder.take();
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vec.push(regs);
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builder.set(vec);
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}
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#[inline]
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fn output_builder_finish(&mut self, builder: &InstOutputBuilder) -> InstOutput {
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builder.take()
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}
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#[inline]
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fn temp_writable_reg(&mut self, ty: Type) -> WritableReg {
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let value_regs = self.lower_ctx.alloc_tmp(ty);
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value_regs.only_reg().unwrap()
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}
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#[inline]
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fn is_valid_reg(&mut self, reg: Reg) -> bool {
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use crate::machinst::valueregs::InvalidSentinel;
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!reg.is_invalid_sentinel()
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}
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#[inline]
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fn invalid_reg(&mut self) -> Reg {
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use crate::machinst::valueregs::InvalidSentinel;
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Reg::invalid_sentinel()
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}
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#[inline]
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fn mark_value_used(&mut self, val: Value) {
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self.lower_ctx.increment_lowered_uses(val);
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}
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#[inline]
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fn put_in_reg(&mut self, val: Value) -> Reg {
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self.put_in_regs(val).only_reg().unwrap()
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}
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#[inline]
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fn put_in_regs(&mut self, val: Value) -> ValueRegs {
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// If the value is a constant, then (re)materialize it at each
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// use. This lowers register pressure. (Only do this if we are
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// not using egraph-based compilation; the egraph framework
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// more efficiently rematerializes constants where needed.)
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if !(self.backend.flags().use_egraphs()
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&& self.backend.flags().opt_level() != OptLevel::None)
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{
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let inputs = self.lower_ctx.get_value_as_source_or_const(val);
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if inputs.constant.is_some() {
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let insn = match inputs.inst {
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InputSourceInst::UniqueUse(insn, 0) => Some(insn),
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InputSourceInst::Use(insn, 0) => Some(insn),
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_ => None,
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};
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if let Some(insn) = insn {
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if let Some(regs) = self.backend.lower(self.lower_ctx, insn) {
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assert!(regs.len() == 1);
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return regs[0];
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}
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}
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}
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}
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self.lower_ctx.put_value_in_regs(val)
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}
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#[inline]
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fn ensure_in_vreg(&mut self, reg: Reg, ty: Type) -> Reg {
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self.lower_ctx.ensure_in_vreg(reg, ty)
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}
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#[inline]
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fn value_regs_get(&mut self, regs: ValueRegs, i: usize) -> Reg {
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regs.regs()[i]
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}
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#[inline]
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fn value_regs_len(&mut self, regs: ValueRegs) -> usize {
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regs.regs().len()
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}
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#[inline]
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fn value_list_slice(&mut self, list: ValueList) -> ValueSlice {
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(list, 0)
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}
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#[inline]
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fn value_slice_empty(&mut self, slice: ValueSlice) -> Option<()> {
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let (list, off) = slice;
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if off >= list.len(&self.lower_ctx.dfg().value_lists) {
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Some(())
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} else {
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None
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}
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}
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#[inline]
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fn value_slice_unwrap(&mut self, slice: ValueSlice) -> Option<(Value, ValueSlice)> {
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let (list, off) = slice;
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if let Some(val) = list.get(off, &self.lower_ctx.dfg().value_lists) {
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Some((val, (list, off + 1)))
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} else {
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None
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}
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}
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#[inline]
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fn value_slice_len(&mut self, slice: ValueSlice) -> usize {
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let (list, off) = slice;
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list.len(&self.lower_ctx.dfg().value_lists) - off
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}
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#[inline]
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fn value_slice_get(&mut self, slice: ValueSlice, idx: usize) -> Value {
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let (list, off) = slice;
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list.get(off + idx, &self.lower_ctx.dfg().value_lists)
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.unwrap()
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}
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#[inline]
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fn writable_reg_to_reg(&mut self, r: WritableReg) -> Reg {
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r.to_reg()
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}
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#[inline]
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fn inst_results(&mut self, inst: Inst) -> ValueSlice {
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(self.lower_ctx.dfg().inst_results_list(inst), 0)
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}
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#[inline]
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fn first_result(&mut self, inst: Inst) -> Option<Value> {
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self.lower_ctx.dfg().inst_results(inst).first().copied()
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}
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#[inline]
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fn inst_data(&mut self, inst: Inst) -> InstructionData {
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self.lower_ctx.dfg().insts[inst]
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}
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#[inline]
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fn def_inst(&mut self, val: Value) -> Option<Inst> {
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self.lower_ctx.dfg().value_def(val).inst()
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}
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fn zero_value(&mut self, value: Value) -> Option<Value> {
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let insn = self.def_inst(value);
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if insn.is_some() {
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let insn = insn.unwrap();
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let inst_data = self.lower_ctx.data(insn);
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match inst_data {
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InstructionData::Unary {
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opcode: Opcode::Splat,
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arg,
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} => {
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let arg = arg.clone();
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return self.zero_value(arg);
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}
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InstructionData::UnaryConst {
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opcode: Opcode::Vconst,
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constant_handle,
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} => {
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let constant_data =
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self.lower_ctx.get_constant_data(*constant_handle).clone();
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if constant_data.into_vec().iter().any(|&x| x != 0) {
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return None;
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} else {
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return Some(value);
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}
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}
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InstructionData::UnaryImm { imm, .. } => {
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if imm.bits() == 0 {
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return Some(value);
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} else {
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return None;
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}
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}
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InstructionData::UnaryIeee32 { imm, .. } => {
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if imm.bits() == 0 {
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return Some(value);
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} else {
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return None;
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}
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}
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InstructionData::UnaryIeee64 { imm, .. } => {
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if imm.bits() == 0 {
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return Some(value);
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} else {
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return None;
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}
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}
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_ => None,
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}
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} else {
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None
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}
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}
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fn avoid_div_traps(&mut self) -> bool {
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self.backend.flags().avoid_div_traps()
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}
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#[inline]
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fn tls_model(&mut self, _: Type) -> TlsModel {
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self.backend.flags().tls_model()
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}
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#[inline]
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fn tls_model_is_elf_gd(&mut self) -> Option<()> {
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if self.backend.flags().tls_model() == TlsModel::ElfGd {
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Some(())
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} else {
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None
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}
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}
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#[inline]
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fn tls_model_is_macho(&mut self) -> Option<()> {
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if self.backend.flags().tls_model() == TlsModel::Macho {
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Some(())
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} else {
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None
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}
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}
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#[inline]
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fn tls_model_is_coff(&mut self) -> Option<()> {
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if self.backend.flags().tls_model() == TlsModel::Coff {
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Some(())
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} else {
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None
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}
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}
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#[inline]
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fn preserve_frame_pointers(&mut self) -> Option<()> {
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if self.backend.flags().preserve_frame_pointers() {
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Some(())
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} else {
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None
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}
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}
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#[inline]
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fn func_ref_data(&mut self, func_ref: FuncRef) -> (SigRef, ExternalName, RelocDistance) {
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let funcdata = &self.lower_ctx.dfg().ext_funcs[func_ref];
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(
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funcdata.signature,
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funcdata.name.clone(),
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funcdata.reloc_distance(),
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)
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}
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#[inline]
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fn box_external_name(&mut self, extname: ExternalName) -> BoxExternalName {
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Box::new(extname)
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}
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#[inline]
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fn symbol_value_data(
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&mut self,
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global_value: GlobalValue,
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) -> Option<(ExternalName, RelocDistance, i64)> {
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let (name, reloc, offset) = self.lower_ctx.symbol_value_data(global_value)?;
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Some((name.clone(), reloc, offset))
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}
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#[inline]
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fn reloc_distance_near(&mut self, dist: RelocDistance) -> Option<()> {
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if dist == RelocDistance::Near {
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Some(())
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} else {
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None
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}
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}
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#[inline]
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fn u128_from_immediate(&mut self, imm: Immediate) -> Option<u128> {
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let bytes = self.lower_ctx.get_immediate_data(imm).as_slice();
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Some(u128::from_le_bytes(bytes.try_into().ok()?))
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}
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#[inline]
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fn vec_mask_from_immediate(&mut self, imm: Immediate) -> Option<VecMask> {
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let data = self.lower_ctx.get_immediate_data(imm);
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if data.len() == 16 {
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Some(Vec::from(data.as_slice()))
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} else {
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None
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}
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}
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#[inline]
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fn u64_from_constant(&mut self, constant: Constant) -> Option<u64> {
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let bytes = self.lower_ctx.get_constant_data(constant).as_slice();
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Some(u64::from_le_bytes(bytes.try_into().ok()?))
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}
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#[inline]
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fn u128_from_constant(&mut self, constant: Constant) -> Option<u128> {
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let bytes = self.lower_ctx.get_constant_data(constant).as_slice();
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Some(u128::from_le_bytes(bytes.try_into().ok()?))
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}
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#[inline]
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fn emit_u64_le_const(&mut self, value: u64) -> VCodeConstant {
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let data = VCodeConstantData::U64(value.to_le_bytes());
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self.lower_ctx.use_constant(data)
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}
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#[inline]
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fn emit_u128_le_const(&mut self, value: u128) -> VCodeConstant {
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let data = VCodeConstantData::Generated(value.to_le_bytes().as_slice().into());
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self.lower_ctx.use_constant(data)
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}
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#[inline]
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fn const_to_vconst(&mut self, constant: Constant) -> VCodeConstant {
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self.lower_ctx.use_constant(VCodeConstantData::Pool(
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constant,
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self.lower_ctx.get_constant_data(constant).clone(),
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))
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}
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fn only_writable_reg(&mut self, regs: WritableValueRegs) -> Option<WritableReg> {
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regs.only_reg()
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}
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fn writable_regs_get(&mut self, regs: WritableValueRegs, idx: usize) -> WritableReg {
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regs.regs()[idx]
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}
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fn abi_num_args(&mut self, abi: Sig) -> usize {
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self.lower_ctx.sigs().num_args(abi)
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}
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fn abi_get_arg(&mut self, abi: Sig, idx: usize) -> ABIArg {
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self.lower_ctx.sigs().get_arg(abi, idx)
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}
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|
|
fn abi_num_rets(&mut self, abi: Sig) -> usize {
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self.lower_ctx.sigs().num_rets(abi)
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}
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|
|
fn abi_get_ret(&mut self, abi: Sig, idx: usize) -> ABIArg {
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self.lower_ctx.sigs().get_ret(abi, idx)
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}
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|
fn abi_ret_arg(&mut self, abi: Sig) -> Option<ABIArg> {
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|
self.lower_ctx.sigs().get_ret_arg(abi)
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}
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|
|
fn abi_no_ret_arg(&mut self, abi: Sig) -> Option<()> {
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|
if let Some(_) = self.lower_ctx.sigs().get_ret_arg(abi) {
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|
None
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|
} else {
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|
Some(())
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|
}
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}
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|
|
|
fn abi_sized_stack_arg_space(&mut self, abi: Sig) -> i64 {
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|
self.lower_ctx.sigs()[abi].sized_stack_arg_space()
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|
}
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|
|
fn abi_sized_stack_ret_space(&mut self, abi: Sig) -> i64 {
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|
self.lower_ctx.sigs()[abi].sized_stack_ret_space()
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|
}
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|
|
fn abi_arg_only_slot(&mut self, arg: &ABIArg) -> Option<ABIArgSlot> {
|
|
match arg {
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|
&ABIArg::Slots { ref slots, .. } => {
|
|
if slots.len() == 1 {
|
|
Some(slots[0])
|
|
} else {
|
|
None
|
|
}
|
|
}
|
|
_ => None,
|
|
}
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|
}
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|
|
|
fn abi_arg_struct_pointer(&mut self, arg: &ABIArg) -> Option<(ABIArgSlot, i64, u64)> {
|
|
match arg {
|
|
&ABIArg::StructArg {
|
|
pointer,
|
|
offset,
|
|
size,
|
|
..
|
|
} => {
|
|
if let Some(pointer) = pointer {
|
|
Some((pointer, offset, size))
|
|
} else {
|
|
None
|
|
}
|
|
}
|
|
_ => None,
|
|
}
|
|
}
|
|
|
|
fn abi_arg_implicit_pointer(&mut self, arg: &ABIArg) -> Option<(ABIArgSlot, i64, Type)> {
|
|
match arg {
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|
&ABIArg::ImplicitPtrArg {
|
|
pointer,
|
|
offset,
|
|
ty,
|
|
..
|
|
} => Some((pointer, offset, ty)),
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|
_ => None,
|
|
}
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|
}
|
|
|
|
fn abi_stackslot_addr(
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|
&mut self,
|
|
dst: WritableReg,
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|
stack_slot: StackSlot,
|
|
offset: Offset32,
|
|
) -> MInst {
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|
let offset = u32::try_from(i32::from(offset)).unwrap();
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|
self.lower_ctx
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|
.abi()
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|
.sized_stackslot_addr(stack_slot, offset, dst)
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|
}
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|
|
|
fn abi_dynamic_stackslot_addr(
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|
&mut self,
|
|
dst: WritableReg,
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|
stack_slot: DynamicStackSlot,
|
|
) -> MInst {
|
|
assert!(self
|
|
.lower_ctx
|
|
.abi()
|
|
.dynamic_stackslot_offsets()
|
|
.is_valid(stack_slot));
|
|
self.lower_ctx.abi().dynamic_stackslot_addr(stack_slot, dst)
|
|
}
|
|
|
|
fn real_reg_to_reg(&mut self, reg: RealReg) -> Reg {
|
|
Reg::from(reg)
|
|
}
|
|
|
|
fn real_reg_to_writable_reg(&mut self, reg: RealReg) -> WritableReg {
|
|
Writable::from_reg(Reg::from(reg))
|
|
}
|
|
|
|
fn is_sinkable_inst(&mut self, val: Value) -> Option<Inst> {
|
|
let input = self.lower_ctx.get_value_as_source_or_const(val);
|
|
|
|
if let InputSourceInst::UniqueUse(inst, _) = input.inst {
|
|
Some(inst)
|
|
} else {
|
|
None
|
|
}
|
|
}
|
|
|
|
#[inline]
|
|
fn sink_inst(&mut self, inst: Inst) {
|
|
self.lower_ctx.sink_inst(inst);
|
|
}
|
|
|
|
#[inline]
|
|
fn maybe_uextend(&mut self, value: Value) -> Option<Value> {
|
|
if let Some(def_inst) = self.def_inst(value) {
|
|
if let InstructionData::Unary {
|
|
opcode: Opcode::Uextend,
|
|
arg,
|
|
} = self.lower_ctx.data(def_inst)
|
|
{
|
|
return Some(*arg);
|
|
}
|
|
}
|
|
|
|
Some(value)
|
|
}
|
|
|
|
#[inline]
|
|
fn preg_to_reg(&mut self, preg: PReg) -> Reg {
|
|
preg.into()
|
|
}
|
|
|
|
#[inline]
|
|
fn gen_move(&mut self, ty: Type, dst: WritableReg, src: Reg) -> MInst {
|
|
MInst::gen_move(dst, src, ty)
|
|
}
|
|
|
|
/// Generate the return instruction.
|
|
fn gen_return(&mut self, (list, off): ValueSlice) {
|
|
let rets = (off..list.len(&self.lower_ctx.dfg().value_lists))
|
|
.map(|ix| {
|
|
let val = list.get(ix, &self.lower_ctx.dfg().value_lists).unwrap();
|
|
self.put_in_regs(val)
|
|
})
|
|
.collect();
|
|
self.lower_ctx.gen_return(rets);
|
|
}
|
|
|
|
/// Same as `shuffle32_from_imm`, but for 64-bit lane shuffles.
|
|
fn shuffle64_from_imm(&mut self, imm: Immediate) -> Option<(u8, u8)> {
|
|
use crate::machinst::isle::shuffle_imm_as_le_lane_idx;
|
|
|
|
let bytes = self.lower_ctx.get_immediate_data(imm).as_slice();
|
|
Some((
|
|
shuffle_imm_as_le_lane_idx(8, &bytes[0..8])?,
|
|
shuffle_imm_as_le_lane_idx(8, &bytes[8..16])?,
|
|
))
|
|
}
|
|
|
|
/// Attempts to interpret the shuffle immediate `imm` as a shuffle of
|
|
/// 32-bit lanes, returning four integers, each of which is less than 8,
|
|
/// which represents a permutation of 32-bit lanes as specified by
|
|
/// `imm`.
|
|
///
|
|
/// For example the shuffle immediate
|
|
///
|
|
/// `0 1 2 3 8 9 10 11 16 17 18 19 24 25 26 27`
|
|
///
|
|
/// would return `Some((0, 2, 4, 6))`.
|
|
fn shuffle32_from_imm(&mut self, imm: Immediate) -> Option<(u8, u8, u8, u8)> {
|
|
use crate::machinst::isle::shuffle_imm_as_le_lane_idx;
|
|
|
|
let bytes = self.lower_ctx.get_immediate_data(imm).as_slice();
|
|
Some((
|
|
shuffle_imm_as_le_lane_idx(4, &bytes[0..4])?,
|
|
shuffle_imm_as_le_lane_idx(4, &bytes[4..8])?,
|
|
shuffle_imm_as_le_lane_idx(4, &bytes[8..12])?,
|
|
shuffle_imm_as_le_lane_idx(4, &bytes[12..16])?,
|
|
))
|
|
}
|
|
|
|
/// Same as `shuffle32_from_imm`, but for 16-bit lane shuffles.
|
|
fn shuffle16_from_imm(
|
|
&mut self,
|
|
imm: Immediate,
|
|
) -> Option<(u8, u8, u8, u8, u8, u8, u8, u8)> {
|
|
use crate::machinst::isle::shuffle_imm_as_le_lane_idx;
|
|
let bytes = self.lower_ctx.get_immediate_data(imm).as_slice();
|
|
Some((
|
|
shuffle_imm_as_le_lane_idx(2, &bytes[0..2])?,
|
|
shuffle_imm_as_le_lane_idx(2, &bytes[2..4])?,
|
|
shuffle_imm_as_le_lane_idx(2, &bytes[4..6])?,
|
|
shuffle_imm_as_le_lane_idx(2, &bytes[6..8])?,
|
|
shuffle_imm_as_le_lane_idx(2, &bytes[8..10])?,
|
|
shuffle_imm_as_le_lane_idx(2, &bytes[10..12])?,
|
|
shuffle_imm_as_le_lane_idx(2, &bytes[12..14])?,
|
|
shuffle_imm_as_le_lane_idx(2, &bytes[14..16])?,
|
|
))
|
|
}
|
|
|
|
fn safe_divisor_from_imm64(&mut self, ty: Type, val: Imm64) -> Option<u64> {
|
|
let minus_one = if ty.bytes() == 8 {
|
|
-1
|
|
} else {
|
|
(1 << (ty.bytes() * 8)) - 1
|
|
};
|
|
let bits = val.bits() & minus_one;
|
|
if bits == 0 || bits == minus_one {
|
|
None
|
|
} else {
|
|
Some(bits as u64)
|
|
}
|
|
}
|
|
};
|
|
}
|
|
|
|
/// Returns the `size`-byte lane referred to by the shuffle immediate specified
|
|
/// in `bytes`.
|
|
///
|
|
/// This helper is used by `shuffleNN_from_imm` above and is used to interpret a
|
|
/// byte-based shuffle as a higher-level shuffle of bigger lanes. This will see
|
|
/// if the `bytes` specified, which must have `size` length, specifies a lane in
|
|
/// vectors aligned to a `size`-byte boundary.
|
|
///
|
|
/// Returns `None` if `bytes` doesn't specify a `size`-byte lane aligned
|
|
/// appropriately, or returns `Some(n)` where `n` is the index of the lane being
|
|
/// shuffled.
|
|
pub fn shuffle_imm_as_le_lane_idx(size: u8, bytes: &[u8]) -> Option<u8> {
|
|
assert_eq!(bytes.len(), usize::from(size));
|
|
|
|
// The first index in `bytes` must be aligned to a `size` boundary for the
|
|
// bytes to be a valid specifier for a lane of `size` bytes.
|
|
if bytes[0] % size != 0 {
|
|
return None;
|
|
}
|
|
|
|
// Afterwards the bytes must all be one larger than the prior to specify a
|
|
// contiguous sequence of bytes that's being shuffled. Basically `bytes`
|
|
// must refer to the entire `size`-byte lane, in little-endian order.
|
|
for i in 0..size - 1 {
|
|
let idx = usize::from(i);
|
|
if bytes[idx] + 1 != bytes[idx + 1] {
|
|
return None;
|
|
}
|
|
}
|
|
|
|
// All of the `bytes` are in-order, meaning that this is a valid shuffle
|
|
// immediate to specify a lane of `size` bytes. The index, when viewed as
|
|
// `size`-byte immediates, will be the first byte divided by the byte size.
|
|
Some(bytes[0] / size)
|
|
}
|
|
|
|
/// Helpers specifically for machines that use ABICaller.
|
|
#[macro_export]
|
|
#[doc(hidden)]
|
|
macro_rules! isle_prelude_caller_methods {
|
|
($abispec:ty, $abicaller:ty) => {
|
|
fn gen_call(
|
|
&mut self,
|
|
sig_ref: SigRef,
|
|
extname: ExternalName,
|
|
dist: RelocDistance,
|
|
args @ (inputs, off): ValueSlice,
|
|
) -> InstOutput {
|
|
let caller_conv = self.lower_ctx.abi().call_conv(self.lower_ctx.sigs());
|
|
let sig = &self.lower_ctx.dfg().signatures[sig_ref];
|
|
let num_rets = sig.returns.len();
|
|
let abi = self.lower_ctx.sigs().abi_sig_for_sig_ref(sig_ref);
|
|
let caller = <$abicaller>::from_func(
|
|
self.lower_ctx.sigs(),
|
|
sig_ref,
|
|
&extname,
|
|
dist,
|
|
caller_conv,
|
|
self.backend.flags().clone(),
|
|
)
|
|
.unwrap();
|
|
|
|
assert_eq!(
|
|
inputs.len(&self.lower_ctx.dfg().value_lists) - off,
|
|
sig.params.len()
|
|
);
|
|
|
|
self.gen_call_common(abi, num_rets, caller, args)
|
|
}
|
|
|
|
fn gen_call_indirect(
|
|
&mut self,
|
|
sig_ref: SigRef,
|
|
val: Value,
|
|
args @ (inputs, off): ValueSlice,
|
|
) -> InstOutput {
|
|
let caller_conv = self.lower_ctx.abi().call_conv(self.lower_ctx.sigs());
|
|
let ptr = self.put_in_reg(val);
|
|
let sig = &self.lower_ctx.dfg().signatures[sig_ref];
|
|
let num_rets = sig.returns.len();
|
|
let abi = self.lower_ctx.sigs().abi_sig_for_sig_ref(sig_ref);
|
|
let caller = <$abicaller>::from_ptr(
|
|
self.lower_ctx.sigs(),
|
|
sig_ref,
|
|
ptr,
|
|
Opcode::CallIndirect,
|
|
caller_conv,
|
|
self.backend.flags().clone(),
|
|
)
|
|
.unwrap();
|
|
|
|
assert_eq!(
|
|
inputs.len(&self.lower_ctx.dfg().value_lists) - off,
|
|
sig.params.len()
|
|
);
|
|
|
|
self.gen_call_common(abi, num_rets, caller, args)
|
|
}
|
|
};
|
|
}
|
|
|
|
/// Helpers for the above ISLE prelude implementations. Meant to go
|
|
/// inside the `impl` for the context type, not the trait impl.
|
|
#[macro_export]
|
|
#[doc(hidden)]
|
|
macro_rules! isle_prelude_method_helpers {
|
|
($abicaller:ty) => {
|
|
fn gen_call_common(
|
|
&mut self,
|
|
abi: Sig,
|
|
num_rets: usize,
|
|
mut caller: $abicaller,
|
|
(inputs, off): ValueSlice,
|
|
) -> InstOutput {
|
|
caller.emit_stack_pre_adjust(self.lower_ctx);
|
|
|
|
let num_args = self.lower_ctx.sigs().num_args(abi);
|
|
|
|
assert_eq!(
|
|
inputs.len(&self.lower_ctx.dfg().value_lists) - off,
|
|
num_args
|
|
);
|
|
let mut arg_regs = vec![];
|
|
for i in 0..num_args {
|
|
let input = inputs
|
|
.get(off + i, &self.lower_ctx.dfg().value_lists)
|
|
.unwrap();
|
|
arg_regs.push(self.put_in_regs(input));
|
|
}
|
|
for (i, arg_regs) in arg_regs.iter().enumerate() {
|
|
caller.emit_copy_regs_to_buffer(self.lower_ctx, i, *arg_regs);
|
|
}
|
|
for (i, arg_regs) in arg_regs.iter().enumerate() {
|
|
for inst in caller.gen_arg(self.lower_ctx, i, *arg_regs) {
|
|
self.lower_ctx.emit(inst);
|
|
}
|
|
}
|
|
|
|
// Handle retvals prior to emitting call, so the
|
|
// constraints are on the call instruction; but buffer the
|
|
// instructions till after the call.
|
|
let mut outputs = InstOutput::new();
|
|
let mut retval_insts: crate::machinst::abi::SmallInstVec<_> = smallvec::smallvec![];
|
|
// We take the *last* `num_rets` returns of the sig:
|
|
// this skips a StructReturn, if any, that is present.
|
|
let sigdata_num_rets = self.lower_ctx.sigs().num_rets(abi);
|
|
debug_assert!(num_rets <= sigdata_num_rets);
|
|
for i in (sigdata_num_rets - num_rets)..sigdata_num_rets {
|
|
// Borrow `sigdata` again so we don't hold a `self`
|
|
// borrow across the `&mut self` arg to
|
|
// `abi_arg_slot_regs()` below.
|
|
let ret = self.lower_ctx.sigs().get_ret(abi, i);
|
|
let retval_regs = self.abi_arg_slot_regs(&ret).unwrap();
|
|
retval_insts.extend(
|
|
caller
|
|
.gen_retval(self.lower_ctx, i, retval_regs.clone())
|
|
.into_iter(),
|
|
);
|
|
outputs.push(valueregs::non_writable_value_regs(retval_regs));
|
|
}
|
|
|
|
caller.emit_call(self.lower_ctx);
|
|
|
|
for inst in retval_insts {
|
|
self.lower_ctx.emit(inst);
|
|
}
|
|
|
|
caller.emit_stack_post_adjust(self.lower_ctx);
|
|
|
|
outputs
|
|
}
|
|
|
|
fn abi_arg_slot_regs(&mut self, arg: &ABIArg) -> Option<WritableValueRegs> {
|
|
match arg {
|
|
&ABIArg::Slots { ref slots, .. } => match slots.len() {
|
|
1 => {
|
|
let a = self.temp_writable_reg(slots[0].get_type());
|
|
Some(WritableValueRegs::one(a))
|
|
}
|
|
2 => {
|
|
let a = self.temp_writable_reg(slots[0].get_type());
|
|
let b = self.temp_writable_reg(slots[1].get_type());
|
|
Some(WritableValueRegs::two(a, b))
|
|
}
|
|
_ => panic!("Expected to see one or two slots only from {:?}", arg),
|
|
},
|
|
_ => None,
|
|
}
|
|
}
|
|
};
|
|
}
|
|
|
|
/// This structure is used to implement the ISLE-generated `Context` trait and
|
|
/// internally has a temporary reference to a machinst `LowerCtx`.
|
|
pub(crate) struct IsleContext<'a, 'b, I, B>
|
|
where
|
|
I: VCodeInst,
|
|
B: LowerBackend,
|
|
{
|
|
pub lower_ctx: &'a mut Lower<'b, I>,
|
|
pub backend: &'a B,
|
|
}
|