5ae8575296
* x64: Take SIGFPE signals for divide traps Prior to this commit Wasmtime would configure `avoid_div_traps=true` unconditionally for Cranelift. This, for the division-based instructions, would change emitted code to explicitly trap on trap conditions instead of letting the `div` x86 instruction trap. There's no specific reason for Wasmtime, however, to specifically avoid traps in the `div` instruction. This means that the extra generated branches on x86 aren't necessary since the `div` and `idiv` instructions already trap for similar conditions as wasm requires. This commit instead disables the `avoid_div_traps` setting for Wasmtime's usage of Cranelift. Subsequently the codegen rules were updated slightly: * When `avoid_div_traps=true`, traps are no longer emitted for `div` instructions. * The `udiv`/`urem` instructions now list their trap as divide-by-zero instead of integer overflow. * The lowering for `sdiv` was updated to still explicitly check for zero but the integer overflow case is deferred to the instruction itself. * The lowering of `srem` no longer checks for zero and the listed trap for the `div` instruction is a divide-by-zero. This means that the codegen for `udiv` and `urem` no longer have any branches. The codegen for `sdiv` removes one branch but keeps the zero-check to differentiate the two kinds of traps. The codegen for `srem` removes one branch but keeps the -1 check since the semantics of `srem` mismatch with the semantics of `idiv` with a -1 divisor (specifically for INT_MIN). This is unlikely to have really all that much of a speedup but was something I noticed during #6008 which seemed like it'd be good to clean up. Plus Wasmtime's signal handling was already set up to catch `SIGFPE`, it was just never firing. * Remove the `avoid_div_traps` cranelift setting With no known users currently removing this should be possible and helps simplify the x64 backend. * x64: GC more support for avoid_div_traps Remove the `validate_sdiv_divisor*` pseudo-instructions and clean up some of the ISLE rules now that `div` is allowed to itself trap unconditionally. * x64: Store div trap code in instruction itself * Keep divisors in registers, not in memory Don't accidentally fold multiple traps together * Handle EXC_ARITHMETIC on macos * Update emit tests * Update winch and tests
280 lines
4.7 KiB
Plaintext
280 lines
4.7 KiB
Plaintext
test compile precise-output
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target x86_64
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function %f1(i8, i8) -> i8 {
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block0(v0: i8, v1: i8):
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v2 = srem v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movq %rdi, %rax
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; cbw %al, %al
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; checked_srem_seq %al, %sil, %al
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; shrq $8, %rax, %rax
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movq %rdi, %rax
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; cbtw
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; cmpb $0xff, %sil
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; jne 0x1d
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; movl $0, %eax
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; jmp 0x20
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; idivb %sil ; trap: int_divz
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; shrq $8, %rax
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f2(i16, i16) -> i16 {
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block0(v0: i16, v1: i16):
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v2 = srem v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movq %rdi, %rax
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; cwd %ax, %dx
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; checked_srem_seq %ax, %dx, %si, %ax, %dx
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; movq %rdx, %rax
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movq %rdi, %rax
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; cwtd
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; cmpw $-1, %si
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; jne 0x1d
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; movl $0, %edx
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; jmp 0x20
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; idivw %si ; trap: int_divz
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; movq %rdx, %rax
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f3(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = srem v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movq %rdi, %rax
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; cdq %eax, %edx
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; checked_srem_seq %eax, %edx, %esi, %eax, %edx
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; movq %rdx, %rax
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movq %rdi, %rax
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; cltd
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; cmpl $-1, %esi
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; jne 0x1b
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; movl $0, %edx
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; jmp 0x1d
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; idivl %esi ; trap: int_divz
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; movq %rdx, %rax
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f4(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = srem v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movq %rdi, %rax
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; cqo %rax, %rdx
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; checked_srem_seq %rax, %rdx, %rsi, %rax, %rdx
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; movq %rdx, %rax
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movq %rdi, %rax
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; cqto
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; cmpq $-1, %rsi
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; jne 0x1d
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; movl $0, %edx
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; jmp 0x20
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; idivq %rsi ; trap: int_divz
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; movq %rdx, %rax
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %i8_imm(i8) -> i8 {
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block0(v0: i8):
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v1 = iconst.i8 17
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v2 = srem v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movq %rdi, %rax
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; cbw %al, %al
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; movl $17, %edx
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; idiv %al, %dl, %al ; trap=int_divz
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; shrq $8, %rax, %rax
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movq %rdi, %rax
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; cbtw
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; movl $0x11, %edx
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; idivb %dl ; trap: int_divz
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; shrq $8, %rax
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %i16_imm(i16) -> i16 {
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block0(v0: i16):
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v1 = iconst.i16 17
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v2 = srem v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movq %rdi, %rax
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; cwd %ax, %dx
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; movl $17, %r8d
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; idiv %ax, %dx, %r8w, %ax, %dx ; trap=int_divz
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; movq %rdx, %rax
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movq %rdi, %rax
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; cwtd
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; movl $0x11, %r8d
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; idivw %r8w ; trap: int_divz
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; movq %rdx, %rax
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %i32_imm(i32) -> i32 {
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block0(v0: i32):
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v1 = iconst.i32 17
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v2 = srem v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movq %rdi, %rax
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; cdq %eax, %edx
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; movl $17, %r8d
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; idiv %eax, %edx, %r8d, %eax, %edx ; trap=int_divz
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; movq %rdx, %rax
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movq %rdi, %rax
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; cltd
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; movl $0x11, %r8d
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; idivl %r8d ; trap: int_divz
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; movq %rdx, %rax
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %i64_imm(i64) -> i64 {
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block0(v0: i64):
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v1 = iconst.i64 17
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v2 = srem v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movq %rdi, %rax
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; cqo %rax, %rdx
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; movl $17, %r8d
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; idiv %rax, %rdx, %r8, %rax, %rdx ; trap=int_divz
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; movq %rdx, %rax
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movq %rdi, %rax
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; cqto
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; movl $0x11, %r8d
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; idivq %r8 ; trap: int_divz
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; movq %rdx, %rax
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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