Jakob Stoklund Olesen 6ba604125d Add bitwise ops that invert the second operand. ...

ARM has all of these as scalar integer instructions. Intel has band_not
in SSE and as a scalar in BMI1.

Add the trivial legalization patterns that use a bnot instruction.

2017-07-20 11:20:06 -07:00

..

.gitignore

Initial Sphinx configuration.

2016-01-12 16:51:35 -08:00

compare-llvm.rst

Documentation fixes (#103)

2017-06-22 12:01:32 -07:00

conf.py

Move the 'meta' dir to 'lib/cretonne/meta'.

2016-10-17 14:19:23 -07:00

cton_domain.py

Begin an Intel-specific instruction group.

2017-07-18 11:20:00 -07:00

cton_lexer.py

Allow for special purpose function arguments and return values.

2017-04-17 15:06:30 -07:00

example.c

Update language reference.

2016-01-21 14:25:16 -08:00

example.cton

Track stack slot kinds.

2017-06-16 11:01:22 -07:00

index.rst

Start a design document for the Cretonne register allocator.

2016-11-21 17:00:16 -08:00

langref.rst

Add bitwise ops that invert the second operand.

2017-07-20 11:20:06 -07:00

make.bat

Initial Sphinx configuration.

2016-01-12 16:51:35 -08:00

Makefile

Add a section about implementation limits.

2017-02-24 11:08:15 -08:00

metaref.rst

Add operand register constraints.

2017-01-25 13:35:18 -08:00

regalloc.rst

Documentation fixes (#103)

2017-06-22 12:01:32 -07:00

testing.rst

Documentation fixes (#103)

2017-06-22 12:01:32 -07:00