dd7fa81b20
This commit goes through the `runtests` folder of the `filetests` test suite and ensure that everything which uses simd or float-related instructions on x64 is executed with the baseline support for x86_64 in addition to adding in AVX support. Most of the instructions used have AVX equivalents so this should help test all of the equivalents in addition to the codegen filetests in the x64 folder.
84 lines
2.5 KiB
Plaintext
84 lines
2.5 KiB
Plaintext
test run
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set enable_simd
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target aarch64
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target s390x
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target x86_64
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target x86_64 skylake
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function %ishl_i8x16(i8x16, i32) -> i8x16 {
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block0(v0: i8x16, v1: i32):
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v2 = ishl v0, v1
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return v2
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}
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; run: %ishl_i8x16([0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15], 4) == [0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xa0 0xb0 0xc0 0xd0 0xe0 0xf0]
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; run: %ishl_i8x16([0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15], 12) == [0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xa0 0xb0 0xc0 0xd0 0xe0 0xf0]
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function %ishl_i16x8(i16x8, i32) -> i16x8 {
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block0(v0: i16x8, v1: i32):
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v2 = ishl v0, v1
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return v2
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}
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; run: %ishl_i16x8([1 2 4 8 16 32 64 128], 1) == [2 4 8 16 32 64 128 256]
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; run: %ishl_i16x8([1 2 4 8 16 32 64 128], 17) == [2 4 8 16 32 64 128 256]
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function %ishl_i32x4(i32x4, i32) -> i32x4 {
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block0(v0: i32x4, v1: i32):
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v2 = ishl v0, v1
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return v2
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}
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; run: %ishl_i32x4([1 2 4 8], 1) == [2 4 8 16]
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; run: %ishl_i32x4([1 2 4 8], 33) == [2 4 8 16]
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function %ishl_i64x2(i64x2, i32) -> i64x2 {
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block0(v0: i64x2, v1: i32):
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v2 = ishl v0, v1
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return v2
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}
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; run: %ishl_i64x2([1 2], 1) == [2 4]
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; run: %ishl_i64x2([1 2], 65) == [2 4]
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function %ishl_imm_i64x2(i64x2) -> i64x2 {
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block0(v0: i64x2):
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v2 = ishl_imm v0, 1
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return v2
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}
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; run: %ishl_imm_i64x2([1 0]) == [2 0]
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function %i8x16_shl_const(i8x16) -> i8x16 {
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block0(v0: i8x16):
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v1 = iconst.i32 2
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v2 = ishl v0, v1
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return v2
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}
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; run: %i8x16_shl_const([0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0 0 0 0 0 0 0 0]) == [0x04 0x08 0x10 0x20 0x40 0x80 0 0 0 0 0 0 0 0 0 0]
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function %i16x8_shl_const(i16x8) -> i16x8 {
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block0(v0: i16x8):
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v1 = iconst.i32 4
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v2 = ishl v0, v1
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return v2
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}
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; run: %i16x8_shl_const([0x0001 0x0002 0x0004 0x0008 0x0010 0x0020 0x0040 0x0080]) == [0x0010 0x0020 0x0040 0x0080 0x0100 0x0200 0x0400 0x0800]
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; run: %i16x8_shl_const([0x0100 0x0200 0x0400 0x0800 0x1000 0x2000 0x4000 0x8000]) == [0x1000 0x2000 0x4000 0x8000 0 0 0 0]
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function %i32x4_shl_const(i32x4) -> i32x4 {
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block0(v0: i32x4):
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v1 = iconst.i32 4
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v2 = ishl v0, v1
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return v2
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}
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; run: %i32x4_shl_const([0x00000001 0x00000002 0x00000004 0x00000008]) == [0x00000010 0x00000020 0x00000040 0x00000080]
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; run: %i32x4_shl_const([0x10000000 0x00010000 0xf0000000 0x02000000]) == [0 0x00100000 0 0x20000000]
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function %i64x2_shl_const(i64x2) -> i64x2 {
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block0(v0: i64x2):
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v1 = iconst.i32 32
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v2 = ishl v0, v1
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return v2
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}
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; run: %i64x2_shl_const([0x1 0xf]) == [0x100000000 0xf00000000]
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; run: %i64x2_shl_const([0x100000000 0]) == [0 0]
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