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54a53b7ab733e71f916bb7073a49b6ddebb51a73
wasmtime
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lib
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cretonne
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meta
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isa
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Jakob Stoklund Olesen
377550b835
Add return_reg encodings for RISC-V.
2017-02-21 16:29:23 -08:00
..
arm32
Generate register class descriptors.
2017-01-20 14:23:06 -08:00
arm64
Generate register class descriptors.
2017-01-20 14:23:06 -08:00
intel
Generate register class descriptors.
2017-01-20 14:23:06 -08:00
riscv
Add return_reg encodings for RISC-V.
2017-02-21 16:29:23 -08:00
__init__.py
Add stubs for Intel and ARM architectures.
2016-11-11 11:32:05 -08:00