5336bbd4cc
Add a Stack() class for specifying operand constraints for values on the stack. Add encoding recipes for RISC-V spill and fill instructions. Don't implement the encoding recipe functions yet since we don't have the stack slot layout yet.
355 lines
12 KiB
Python
355 lines
12 KiB
Python
"""
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Register set definitions
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------------------------
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Each ISA defines a separate register set that is used by the register allocator
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and the final binary encoding of machine code.
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The CPU registers are first divided into disjoint register banks, represented
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by a `RegBank` instance. Registers in different register banks never interfere
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with each other. A typical CPU will have a general purpose and a floating point
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register bank.
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A register bank consists of a number of *register units* which are the smallest
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indivisible units of allocation and interference. A register unit doesn't
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necessarily correspond to a particular number of bits in a register, it is more
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like a placeholder that can be used to determine of a register is taken or not.
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The register allocator works with *register classes* which can allocate one or
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more register units at a time. A register class allocates more than one
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register unit at a time when its registers are composed of smaller allocatable
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units. For example, the ARM double precision floating point registers are
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composed of two single precision registers.
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"""
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from __future__ import absolute_import
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from . import is_power_of_two, next_power_of_two
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try:
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from typing import Sequence, Tuple, List, Dict, Any, TYPE_CHECKING # noqa
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if TYPE_CHECKING:
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from .isa import TargetISA # noqa
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# A tuple uniquely identifying a register class inside a register bank.
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# (count, width, start)
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RCTup = Tuple[int, int, int]
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except ImportError:
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pass
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# The number of 32-bit elements in a register unit mask
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MASK_LEN = 3
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# The maximum total number of register units allowed.
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# This limit can be raised by also adjusting the RegUnitMask type in
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# src/isa/registers.rs.
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MAX_UNITS = MASK_LEN * 32
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class RegBank(object):
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"""
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A register bank belonging to an ISA.
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A register bank controls a set of *register units* disjoint from all the
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other register banks in the ISA. The register units are numbered uniquely
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within the target ISA, and the units in a register bank form a contiguous
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sequence starting from a sufficiently aligned point that their low bits can
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be used directly when encoding machine code instructions.
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Register units can be given generated names like `r0`, `r1`, ..., or a
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tuple of special register unit names can be provided.
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:param name: Name of this register bank.
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:param doc: Documentation string.
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:param units: Number of register units.
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:param prefix: Prefix for generated unit names.
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:param names: Special names for the first units. May be shorter than
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`units`, the remaining units are named using `prefix`.
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"""
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def __init__(self, name, isa, doc, units, prefix='r', names=()):
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# type: (str, TargetISA, str, int, str, Sequence[str]) -> None
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self.name = name
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self.isa = isa
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self.first_unit = 0
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self.units = units
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self.prefix = prefix
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self.names = names
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self.classes = list() # type: List[RegClass]
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self.toprcs = list() # type: List[RegClass]
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self.first_toprc_index = None # type: int
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assert len(names) <= units
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if isa.regbanks:
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# Get the next free unit number.
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last = isa.regbanks[-1]
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u = last.first_unit + last.units
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align = units
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if not is_power_of_two(align):
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align = next_power_of_two(align)
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self.first_unit = (u + align - 1) & -align
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self.index = len(isa.regbanks)
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isa.regbanks.append(self)
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def __repr__(self):
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# type: () -> str
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return ('RegBank({}, units={}, first_unit={})'
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.format(self.name, self.units, self.first_unit))
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def finish_regclasses(self):
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# type: () -> None
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"""
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Compute subclasses and the top-level register class.
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Verify that the set of register classes satisfies:
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1. Closed under intersection: The intersection of any two register
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classes in the set is either empty or identical to a member of the
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set.
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2. There are no identical classes under different names.
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3. Classes are sorted topologically such that all subclasses have a
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higher index that the superclass.
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We could reorder classes topologically here instead of just enforcing
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the order, but the ordering tends to fall out naturally anyway.
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"""
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cmap = dict() # type: Dict[RCTup, RegClass]
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for rc in self.classes:
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# All register classes must be given a name.
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assert rc.name, "Anonymous register class found"
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# Check for duplicates.
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tup = rc.rctup()
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if tup in cmap:
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raise AssertionError(
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'{} and {} are identical register classes'
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.format(rc, cmap[tup]))
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cmap[tup] = rc
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# Check intersections and topological order.
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for idx, rc1 in enumerate(self.classes):
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rc1.toprc = rc1
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for rc2 in self.classes[0:idx]:
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itup = rc1.intersect(rc2)
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if itup is None:
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continue
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if itup not in cmap:
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raise AssertionError(
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'intersection of {} and {} missing'
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.format(rc1, rc2))
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irc = cmap[itup]
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# rc1 > rc2, so rc2 can't be the sub-class.
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if irc is rc2:
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raise AssertionError(
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'Bad topological order: {}/{}'
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.format(rc1, rc2))
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if irc is rc1:
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# The intersection of rc1 and rc2 is rc1, so it must be a
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# sub-class.
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rc2.subclasses.append(rc1)
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rc1.toprc = rc2.toprc
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if rc1.is_toprc():
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self.toprcs.append(rc1)
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def unit_by_name(self, name):
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# type: (str) -> int
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"""
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Get a register unit in this bank by name.
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"""
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if name in self.names:
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r = self.names.index(name)
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elif name.startswith(self.prefix):
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r = int(name[len(self.prefix):])
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assert r < self.units, 'Invalid register name: ' + name
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return self.first_unit + r
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class RegClass(object):
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"""
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A register class is a subset of register units in a RegBank along with a
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strategy for allocating registers.
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The *width* parameter determines how many register units are allocated at a
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time. Usually it that is one, but for example the ARM D registers are
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allocated two units at a time. When multiple units are allocated, it is
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always a contiguous set of unit numbers.
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:param bank: The register bank we're allocating from.
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:param count: The maximum number of allocations in this register class. By
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default, the whole register bank can be allocated.
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:param width: How many units to allocate at a time.
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:param start: The first unit to allocate, relative to `bank.first.unit`.
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"""
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def __init__(self, bank, count=None, width=1, start=0):
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# type: (RegBank, int, int, int) -> None
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self.name = None # type: str
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self.index = None # type: int
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self.bank = bank
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self.start = start
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self.width = width
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# This is computed later in `finish_regclasses()`.
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self.subclasses = list() # type: List[RegClass]
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self.toprc = None # type: RegClass
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assert width > 0
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assert start >= 0 and start < bank.units
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if count is None:
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count = bank.units // width
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self.count = count
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bank.classes.append(self)
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def __str__(self):
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# type: () -> str
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return self.name
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def is_toprc(self):
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# type: () -> bool
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"""
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Is this a top-level register class?
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A top-level register class has no sub-classes. This can only be
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answered aster running `finish_regclasses()`.
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"""
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return self.toprc is self
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def rctup(self):
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# type: () -> RCTup
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"""
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Get a tuple that uniquely identifies the registers in this class.
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The tuple can be used as a dictionary key to ensure that there are no
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duplicate register classes.
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"""
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return (self.count, self.width, self.start)
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def intersect(self, other):
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# type: (RegClass) -> RCTup
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"""
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Get a tuple representing the intersction of two register classes.
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Returns `None` if the two classes are disjoint.
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"""
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if self.width != other.width:
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return None
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s_end = self.start + self.count * self.width
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o_end = other.start + other.count * other.width
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if self.start >= o_end or other.start >= s_end:
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return None
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# We have an overlap.
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start = max(self.start, other.start)
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end = min(s_end, o_end)
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count = (end - start) // self.width
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assert count > 0
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return (count, self.width, start)
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def __getitem__(self, sliced):
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# type: (slice) -> RegClass
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"""
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Create a sub-class of a register class using slice notation. The slice
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indexes refer to allocations in the parent register class, not register
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units.
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"""
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assert isinstance(sliced, slice), "RegClass slicing can't be 1 reg"
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# We could add strided sub-classes if needed.
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assert sliced.step is None, 'Subclass striding not supported'
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w = self.width
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s = self.start + sliced.start * w
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c = sliced.stop - sliced.start
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assert c > 1, "Can't have single-register classes"
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return RegClass(self.bank, count=c, width=w, start=s)
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def __getattr__(self, attr):
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# type: (str) -> Register
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"""
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Get a specific register in the class by name.
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For example: `GPR.r5`.
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"""
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return Register(self, self.bank.unit_by_name(attr))
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def mask(self):
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# type: () -> List[int]
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"""
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Compute a bit-mask of the register units allocated by this register
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class.
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Return as a list of 32-bit integers.
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"""
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mask = [0] * MASK_LEN
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start = self.bank.first_unit + self.start
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for a in range(self.count):
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u = start + a * self.width
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b = u % 32
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# We need fancier masking code if a register can straddle mask
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# words. This will only happen with widths that are not powers of
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# two.
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assert b + self.width <= 32, 'Register straddles words'
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mask[u // 32] |= 1 << b
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return mask
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def subclass_mask(self):
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# type: () -> int
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"""
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Compute a bit-mask of subclasses, including self.
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"""
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m = 1 << self.index
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for rc in self.subclasses:
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m |= 1 << rc.index
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return m
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@staticmethod
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def extract_names(globs):
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# type: (Dict[str, Any]) -> None
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"""
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Given a dict mapping name -> object as returned by `globals()`, find
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all the RegClass objects and set their name from the dict key.
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This is used to name a bunch of global variables in a module.
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"""
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for name, obj in globs.items():
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if isinstance(obj, RegClass):
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assert obj.name is None
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obj.name = name
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class Register(object):
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"""
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A specific register in a register class.
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A register is identified by the top-level register class it belongs to and
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its first register unit.
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Specific registers are used to describe constraints on instructions where
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some operands must use a fixed register.
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Register instances can be created with the constructor, or accessed as
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attributes on the register class: `GPR.rcx`.
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"""
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def __init__(self, rc, unit):
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# type: (RegClass, int) -> None
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self.regclass = rc
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self.unit = unit
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class Stack(object):
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"""
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An operand that must be in a stack slot.
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A `Stack` object can be used to indicate an operand constraint for a value
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operand that must live in a stack slot.
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"""
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def __init__(self, rc):
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# type: (RegClass) -> None
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self.regclass = rc
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