Files
wasmtime/cranelift/filetests/filetests/runtests/simd_compare_zero.clif
Trevor Elliott 32a7593c94 cranelift: Remove booleans (#5031)
Remove the boolean types from cranelift, and the associated instructions breduce, bextend, bconst, and bint. Standardize on using 1/0 for the return value from instructions that produce scalar boolean results, and -1/0 for boolean vector elements.

Fixes #3205

Co-authored-by: Afonso Bordado <afonso360@users.noreply.github.com>
Co-authored-by: Ulrich Weigand <ulrich.weigand@de.ibm.com>
Co-authored-by: Chris Fallin <chris@cfallin.org>
2022-10-17 16:00:27 -07:00

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test run
target aarch64
target s390x
function %simd_icmp_eq_i8(i8x16) -> i8x16 {
block0(v0: i8x16):
v1 = iconst.i8 0
v3 = splat.i8x16 v1
v2 = icmp eq v0, v3
return v2
}
; run: %simd_icmp_eq_i8([-1 0 1 100 -1 0 1 100 -1 0 1 100 -1 0 1 100]) == [0 0xff 0 0 0 0xff 0 0 0 0xff 0 0 0 0xff 0 0]
function %simd_icmp_ne_i16(i16x8) -> i16x8 {
block0(v0: i16x8):
v1 = iconst.i16 0
v3 = splat.i16x8 v1
v2 = icmp ne v0, v3
return v2
}
; run: %simd_icmp_ne_i16([-1 0 1 100 -1 0 1 100]) == [0xffff 0 0xffff 0xffff 0xffff 0 0xffff 0xffff]
function %simd_icmp_le_i32(i32x4) -> i32x4 {
block0(v0: i32x4):
v1 = iconst.i32 0
v3 = splat.i32x4 v1
v2 = icmp sle v0, v3
return v2
}
; run: %simd_icmp_le_i32([-1 0 1 100]) == [0xffffffff 0xffffffff 0 0]
function %simd_icmp_ge_i64(i64x2) -> i64x2 {
block0(v0: i64x2):
v1 = iconst.i64 0
v3 = splat.i64x2 v1
v2 = icmp sge v0, v3
return v2
}
; run: %simd_icmp_ge_i64([-1 0]) == [0 0xffffffffffffffff]
; run: %simd_icmp_ge_i64([1 100]) == [0xffffffffffffffff 0xffffffffffffffff]
function %simd_icmp_lt_i8(i8x16) -> i8x16 {
block0(v0: i8x16):
v1 = iconst.i8 0
v3 = splat.i8x16 v1
v2 = icmp slt v0, v3
return v2
}
; run: %simd_icmp_lt_i8([-1 0 1 100 -1 0 1 100 -1 0 1 100 -1 0 1 100]) == [0xff 0 0 0 0xff 0 0 0 0xff 0 0 0 0xff 0 0 0]
function %simd_icmp_gt_i16(i16x8) -> i16x8 {
block0(v0: i16x8):
v1 = iconst.i16 0
v3 = splat.i16x8 v1
v2 = icmp sgt v0, v3
return v2
}
; run: %simd_icmp_gt_i16([-1 0 1 100 -1 0 1 100]) == [0 0 0xffff 0xffff 0 0 0xffff 0xffff]
function %simd_fcmp_eq_f32(f32x4) -> i32x4 {
block0(v0: f32x4):
v1 = f32const 0.0
v3 = splat.f32x4 v1
v2 = fcmp eq v0, v3
return v2
}
; run: %simd_fcmp_eq_f32([-0x1.0 0x0.0 0x1.0 NaN]) == [0 0xffffffff 0 0]
function %simd_fcmp_ne_f64(f64x2) -> i64x2 {
block0(v0: f64x2):
v1 = f64const 0.0
v3 = splat.f64x2 v1
v2 = fcmp ne v0, v3
return v2
}
; run: %simd_fcmp_ne_f64([-0x1.0 0x0.0]) == [0xffffffffffffffff 0]
; run: %simd_fcmp_ne_f64([0x1.0 NaN]) == [0xffffffffffffffff 0xffffffffffffffff]
function %simd_fcmp_le_f32(f32x4) -> i32x4 {
block0(v0: f32x4):
v1 = f32const 0.0
v3 = splat.f32x4 v1
v2 = fcmp le v0, v3
return v2
}
; run: %simd_fcmp_le_f32([-0x1.0 0x0.0 0x1.0 NaN]) == [0xffffffff 0xffffffff 0 0]
function %simd_fcmp_ge_f64(f64x2) -> i64x2 {
block0(v0: f64x2):
v1 = f64const 0.0
v3 = splat.f64x2 v1
v2 = fcmp ge v0, v3
return v2
}
; run: %simd_fcmp_ge_f64([-0x1.0 0x0.0]) == [0 0xffffffffffffffff]
; run: %simd_fcmp_ge_f64([0x1.0 NaN]) == [0xffffffffffffffff 0]
function %simd_fcmp_lt_f32(f32x4) -> i32x4 {
block0(v0: f32x4):
v1 = f32const 0.0
v3 = splat.f32x4 v1
v2 = fcmp lt v0, v3
return v2
}
; run: %simd_fcmp_lt_f32([-0x1.0 0x0.0 0x1.0 NaN]) == [0xffffffff 0 0 0]
function %simd_fcmp_gt_f64(f64x2) -> i64x2 {
block0(v0: f64x2):
v1 = f64const 0.0
v3 = splat.f64x2 v1
v2 = fcmp gt v0, v3
return v2
}
; run: %simd_fcmp_gt_f64([-0x1.0 0x0.0]) == [0 0]
; run: %simd_fcmp_gt_f64([0x1.0 NaN]) == [0xffffffffffffffff 0]
function %simd_icmp_eq_i32(i32x4) -> i32x4 {
block0(v0: i32x4):
v1 = iconst.i32 0
v3 = splat.i32x4 v1
v2 = icmp eq v3, v0
return v2
}
; run: %simd_icmp_eq_i32([1 0 -1 100]) == [0 0xffffffff 0 0]
function %simd_icmp_ne_i64(i64x2) -> i64x2 {
block0(v0: i64x2):
v1 = iconst.i64 0
v3 = splat.i64x2 v1
v2 = icmp ne v3, v0
return v2
}
; run: %simd_icmp_ne_i64([-1 0]) == [0xffffffffffffffff 0]
; run: %simd_icmp_ne_i64([1 100]) == [0xffffffffffffffff 0xffffffffffffffff]
function %simd_icmp_le_i8(i8x16) -> i8x16 {
block0(v0: i8x16):
v1 = iconst.i8 0
v3 = splat.i8x16 v1
v2 = icmp sle v3, v0
return v2
}
; run: %simd_icmp_le_i8([-1 0 1 100 -1 0 1 100 -1 0 1 100 -1 0 1 100]) == [0 0xff 0xff 0xff 0 0xff 0xff 0xff 0 0xff 0xff 0xff 0 0xff 0xff 0xff]
function %simd_icmp_ge_i16(i16x8) -> i16x8 {
block0(v0: i16x8):
v1 = iconst.i16 0
v3 = splat.i16x8 v1
v2 = icmp sge v3, v0
return v2
}
; run: %simd_icmp_ge_i16([-1 0 1 100 -1 0 1 100]) == [0xffff 0xffff 0 0 0xffff 0xffff 0 0]
function %simd_icmp_lt_i32(i32x4) -> i32x4 {
block0(v0: i32x4):
v1 = iconst.i32 0
v3 = splat.i32x4 v1
v2 = icmp slt v3, v0
return v2
}
; run: %simd_icmp_lt_i32([-1 0 1 100]) == [0 0 0xffffffff 0xffffffff]
function %simd_icmp_gt_i64(i64x2) -> i64x2 {
block0(v0: i64x2):
v1 = iconst.i64 0
v3 = splat.i64x2 v1
v2 = icmp sgt v3, v0
return v2
}
; run: %simd_icmp_gt_i64([-1 0]) == [0xffffffffffffffff 0]
; run: %simd_icmp_gt_i64([1 100]) == [0 0]
function %simd_fcmp_eq_f64(f64x2) -> i64x2 {
block0(v0: f64x2):
v1 = f64const 0.0
v3 = splat.f64x2 v1
v2 = fcmp eq v3, v0
return v2
}
; run: %simd_fcmp_eq_f64([-0x1.0 0x0.0]) == [0 0xffffffffffffffff]
; run: %simd_fcmp_eq_f64([0x1.0 NaN]) == [0 0]
function %simd_fcmp_ne_f32(f32x4) -> i32x4 {
block0(v0: f32x4):
v1 = f32const 0.0
v3 = splat.f32x4 v1
v2 = fcmp ne v3, v0
return v2
}
; run: %simd_fcmp_ne_f32([-0x1.0 0x0.0 0x1.0 NaN]) == [0xffffffff 0 0xffffffff 0xffffffff]
function %simd_fcmp_le_f64(f64x2) -> i64x2 {
block0(v0: f64x2):
v1 = f64const 0.0
v3 = splat.f64x2 v1
v2 = fcmp le v3, v0
return v2
}
; run: %simd_fcmp_le_f64([-0x1.0 0x0.0]) == [0 0xffffffffffffffff]
; run: %simd_fcmp_le_f64([0x1.0 NaN]) == [0xffffffffffffffff 0]
function %simd_fcmp_ge_f32(f32x4) -> i32x4 {
block0(v0: f32x4):
v1 = f32const 0.0
v3 = splat.f32x4 v1
v2 = fcmp ge v3, v0
return v2
}
; run: %simd_fcmp_ge_f32([-0x1.0 0x0.0 0x1.0 NaN]) == [0xffffffff 0xffffffff 0 0]
function %simd_fcmp_lt_f64(f64x2) -> i64x2 {
block0(v0: f64x2):
v1 = f64const 0.0
v3 = splat.f64x2 v1
v2 = fcmp lt v3, v0
return v2
}
; run: %simd_fcmp_lt_f64([-0x1.0 0x0.0]) == [0 0]
; run: %simd_fcmp_lt_f64([0x1.0 NaN]) == [0xffffffffffffffff 0]
function %simd_fcmp_gt_f32(f32x4) -> i32x4 {
block0(v0: f32x4):
v1 = f32const 0.0
v3 = splat.f32x4 v1
v2 = fcmp gt v3, v0
return v2
}
; run: %simd_fcmp_gt_f32([-0x1.0 0x0.0 0x1.0 NaN]) == [0xffffffff 0 0 0]