6ecdc2482e
* x64: Improve memory support in `{insert,extract}lane`
This commit improves adds support to Cranelift to emit `pextr{b,w,d,q}`
with a memory destination, merging a store-of-extract operation into one
instruction. Additionally AVX support is added for the `pextr*`
instructions.
I've additionally tried to ensure that codegen tests and runtests exist
for all forms of these instructions too.
* Add missing commas
* Fix tests
138 lines
3.8 KiB
Plaintext
138 lines
3.8 KiB
Plaintext
test interpret
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test run
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target aarch64
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target s390x
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set enable_simd
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target x86_64 has_sse3 has_ssse3 has_sse41
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target x86_64 has_sse3 has_ssse3 has_sse41 has_avx
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function %insertlane_15(i8x16, i8) -> i8x16 {
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block0(v0: i8x16, v1: i8):
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v2 = insertlane v0, v1, 15
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return v2
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}
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; run: %insertlane_15([1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1], 120) == [1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 120]
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function %insertlane_5(i16x8, i16) -> i16x8 {
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block0(v0: i16x8, v1: i16):
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v2 = insertlane v0, v1, 5
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return v2
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}
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; run: %insertlane_5([1 1 1 1 1 1 1 1], 10000) == [1 1 1 1 1 10000 1 1]
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function %insertlane_2(i32x4, i32) -> i32x4 {
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block0(v0: i32x4, v1: i32):
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v2 = insertlane v0, v1, 2
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return v2
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}
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; run: %insertlane_2([1 1 1 1], 100000) == [1 1 100000 1]
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function %insertlane_0(i64x2, i64) -> i64x2 {
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block0(v0: i64x2, v1: i64):
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v2 = insertlane v0, v1, 0
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return v2
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}
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; run: %insertlane_0([1 1], 5000000000) == [5000000000 1]
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function %insertlane_0_in_f64x2(f64x2, f64) -> f64x2 {
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block0(v0: f64x2, v1: f64):
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v2 = insertlane v0, v1, 0
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return v2
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}
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; run: %insertlane_0_in_f64x2([0x1.0 0x2.0], 0x3.0) == [0x3.0 0x2.0]
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function %insertlane_1_in_f64x2(f64x2, f64) -> f64x2 {
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block0(v0: f64x2, v1: f64):
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v2 = insertlane v0, v1, 1
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return v2
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}
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; run: %insertlane_1_in_f64x2([0x1.0 0x2.0], 0x3.0) == [0x1.0 0x3.0]
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function %insertlane_i8x16_through_stack(i8x16, i8) -> i8x16 {
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ss0 = explicit_slot 8
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block0(v0: i8x16, v1: i8):
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v2 = stack_addr.i64 ss0
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store v1, v2
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v3 = load.i8 v2
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v4 = insertlane v0, v3, 1
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return v4
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}
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; run: %insertlane_i8x16_through_stack([1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1], 2) == [1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1]
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function %insertlane_i16x8_through_stack(i16x8, i16) -> i16x8 {
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ss0 = explicit_slot 8
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block0(v0: i16x8, v1: i16):
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v2 = stack_addr.i64 ss0
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store v1, v2
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v3 = load.i16 v2
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v4 = insertlane v0, v3, 2
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return v4
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}
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; run: %insertlane_i16x8_through_stack([1 1 1 1 1 1 1 1], 2) == [1 1 2 1 1 1 1 1]
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function %insertlane_i32x4_through_stack(i32x4, i32) -> i32x4 {
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ss0 = explicit_slot 8
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block0(v0: i32x4, v1: i32):
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v2 = stack_addr.i64 ss0
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store v1, v2
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v3 = load.i32 v2
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v4 = insertlane v0, v3, 3
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return v4
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}
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; run: %insertlane_i32x4_through_stack([1 1 1 1], 2) == [1 1 1 2]
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function %insertlane_i64x2_through_stack(i64x2, i64) -> i64x2 {
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ss0 = explicit_slot 8
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block0(v0: i64x2, v1: i64):
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v2 = stack_addr.i64 ss0
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store v1, v2
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v3 = load.i64 v2
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v4 = insertlane v0, v3, 0
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return v4
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}
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; run: %insertlane_i64x2_through_stack([1 1], 2) == [2 1]
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function %insertlane_f32x4_through_stack(f32x4, f32) -> f32x4 {
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ss0 = explicit_slot 8
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block0(v0: f32x4, v1: f32):
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v2 = stack_addr.i64 ss0
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store v1, v2
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v3 = load.f32 v2
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v4 = insertlane v0, v3, 3
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return v4
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}
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; run: %insertlane_f32x4_through_stack([0x1.0 0x1.0 0x1.0 0x1.0], 0x2.0) == [0x1.0 0x1.0 0x1.0 0x2.0]
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function %insertlane_f32x4_through_stack2(f32x4, f32) -> f32x4 {
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ss0 = explicit_slot 8
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block0(v0: f32x4, v1: f32):
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v2 = stack_addr.i64 ss0
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store v1, v2
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v3 = load.f32 v2
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v4 = insertlane v0, v3, 0
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return v4
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}
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; run: %insertlane_f32x4_through_stack2([0x1.0 0x1.0 0x1.0 0x1.0], 0x2.0) == [0x2.0 0x1.0 0x1.0 0x1.0]
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function %insertlane_f64x2_through_stack(f64x2, f64) -> f64x2 {
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ss0 = explicit_slot 8
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block0(v0: f64x2, v1: f64):
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v2 = stack_addr.i64 ss0
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store v1, v2
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v3 = load.f64 v2
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v4 = insertlane v0, v3, 0
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return v4
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}
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; run: %insertlane_f64x2_through_stack([0x1.0 0x1.0], 0x2.0) == [0x2.0 0x1.0]
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function %insertlane_f64x2_through_stack2(f64x2, f64) -> f64x2 {
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ss0 = explicit_slot 8
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block0(v0: f64x2, v1: f64):
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v2 = stack_addr.i64 ss0
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store v1, v2
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v3 = load.f64 v2
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v4 = insertlane v0, v3, 1
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return v4
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}
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; run: %insertlane_f64x2_through_stack2([0x1.0 0x1.0], 0x2.0) == [0x1.0 0x2.0]
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