dd7fa81b20
This commit goes through the `runtests` folder of the `filetests` test suite and ensure that everything which uses simd or float-related instructions on x64 is executed with the baseline support for x86_64 in addition to adding in AVX support. Most of the instructions used have AVX equivalents so this should help test all of the equivalents in addition to the codegen filetests in the x64 folder.
152 lines
4.7 KiB
Plaintext
152 lines
4.7 KiB
Plaintext
test interpret
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test run
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target x86_64
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target x86_64 has_sse41=false
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set enable_simd
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target x86_64 has_avx
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target aarch64
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target s390x
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target riscv64
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function %floor_f32(f32) -> f32 {
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block0(v0: f32):
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v1 = floor v0
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return v1
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}
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; run: %floor_f32(0x0.5) == 0x0.0
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; run: %floor_f32(0x1.0) == 0x1.0
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; run: %floor_f32(0x1.5) == 0x1.0
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; run: %floor_f32(0x2.9) == 0x1.0p1
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; run: %floor_f32(0x1.1p10) == 0x1.1p10
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; run: %floor_f32(0x1.400000p1) == 0x1.0p1
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; run: %floor_f32(0x1.4cccccp0) == 0x1.0
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; run: %floor_f32(0x1.800000p0) == 0x1.0
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; run: %floor_f32(0x1.b33334p0) == 0x1.0
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; run: %floor_f32(0x1.99999ap-2) == 0x0.0
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; run: %floor_f32(0x1.333334p-1) == 0x0.0
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; run: %floor_f32(0x1.666666p1) == 0x1.0p1
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; Negatives
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; run: %floor_f32(-0x0.5) == -0x1.0
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; run: %floor_f32(-0x1.0) == -0x1.0
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; run: %floor_f32(-0x1.5) == -0x1.0p1
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; run: %floor_f32(-0x2.9) == -0x1.8p1
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; run: %floor_f32(-0x1.1p10) == -0x1.1p10
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; run: %floor_f32(-0x1.333334p-1) == -0x1.0
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; run: %floor_f32(-0x1.99999ap-2) == -0x1.0
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; run: %floor_f32(-0x1.4cccccp0) == -0x1.0p1
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; run: %floor_f32(-0x1.800000p0) == -0x1.0p1
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; run: %floor_f32(-0x1.b33334p0) == -0x1.0p1
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; run: %floor_f32(-0x1.400000p1) == -0x1.8p1
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; run: %floor_f32(-0x1.666666p1) == -0x1.8p1
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; Specials
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; run: %floor_f32(0x0.0) == 0x0.0
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; run: %floor_f32(-0x0.0) == -0x0.0
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; run: %floor_f32(+Inf) == +Inf
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; run: %floor_f32(-Inf) == -Inf
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; F32 Epsilon / Max / Min Positive
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; run: %floor_f32(0x1.000000p-23) == 0x0.0
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; run: %floor_f32(0x1.fffffep127) == 0x1.fffffep127
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; run: %floor_f32(0x1.000000p-126) == 0x0.0
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; F32 Subnormals
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; run: %floor_f32(0x0.800000p-126) == 0x0.0
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; run: %floor_f32(-0x0.800002p-126) == -0x1.0
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; F32 NaN's
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; For NaN's this operation is specified as producing a value that is a NaN
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function %floor_is_nan_f32(f32) -> i32 {
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block0(v0: f32):
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v1 = floor v0
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v2 = fcmp ne v1, v1
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v3 = uextend.i32 v2
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return v3
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}
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; run: %floor_is_nan_f32(+NaN) == 1
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; run: %floor_is_nan_f32(-NaN) == 1
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; run: %floor_is_nan_f32(+NaN:0x0) == 1
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; run: %floor_is_nan_f32(+NaN:0x1) == 1
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; run: %floor_is_nan_f32(+NaN:0x300001) == 1
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; run: %floor_is_nan_f32(-NaN:0x0) == 1
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; run: %floor_is_nan_f32(-NaN:0x1) == 1
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; run: %floor_is_nan_f32(-NaN:0x300001) == 1
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; run: %floor_is_nan_f32(+sNaN:0x1) == 1
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; run: %floor_is_nan_f32(-sNaN:0x1) == 1
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; run: %floor_is_nan_f32(+sNaN:0x200001) == 1
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; run: %floor_is_nan_f32(-sNaN:0x200001) == 1
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function %floor_f64(f64) -> f64 {
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block0(v0: f64):
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v1 = floor v0
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return v1
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}
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; run: %floor_f64(0x0.5) == 0x0.0
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; run: %floor_f64(0x1.0) == 0x1.0
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; run: %floor_f64(0x1.5) == 0x1.0
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; run: %floor_f64(0x2.9) == 0x1.0p1
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; run: %floor_f64(0x1.1p10) == 0x1.1p10
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; run: %floor_f64(0x1.4000000000000p1) == 0x1.0p1
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; run: %floor_f64(0x1.4cccccccccccdp0) == 0x1.0
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; run: %floor_f64(0x1.8000000000000p0) == 0x1.0
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; run: %floor_f64(0x1.b333333333333p0) == 0x1.0
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; run: %floor_f64(0x1.999999999999ap-2) == 0x0.0
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; run: %floor_f64(0x1.3333333333333p-1) == 0x0.0
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; run: %floor_f64(0x1.6666666666666p1) == 0x1.0p1
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; Negatives
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; run: %floor_f64(-0x0.5) == -0x1.0
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; run: %floor_f64(-0x1.0) == -0x1.0
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; run: %floor_f64(-0x1.5) == -0x1.0p1
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; run: %floor_f64(-0x2.9) == -0x1.8p1
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; run: %floor_f64(-0x1.1p10) == -0x1.1p10
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; run: %floor_f64(-0x1.3333333333333p-1) == -0x1.0
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; run: %floor_f64(-0x1.999999999999ap-2) == -0x1.0
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; run: %floor_f64(-0x1.4cccccccccccdp0) == -0x1.0p1
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; run: %floor_f64(-0x1.8000000000000p0) == -0x1.0p1
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; run: %floor_f64(-0x1.b333333333333p0) == -0x1.0p1
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; run: %floor_f64(-0x1.4000000000000p1) == -0x1.8p1
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; run: %floor_f64(-0x1.6666666666666p1) == -0x1.8p1
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; Specials
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; run: %floor_f64(0x0.0) == 0x0.0
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; run: %floor_f64(-0x0.0) == -0x0.0
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; run: %floor_f64(+Inf) == +Inf
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; run: %floor_f64(-Inf) == -Inf
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; F64 Epsilon / Max / Min Positive
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; run: %floor_f64(0x1.0000000000000p-52) == 0x0.0
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; run: %floor_f64(0x1.fffffffffffffp1023) == 0x1.fffffffffffffp1023
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; run: %floor_f64(0x1.0000000000000p-1022) == 0x0.0
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; F64 Subnormals
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; run: %floor_f64(0x0.8000000000000p-1022) == 0x0.0
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; run: %floor_f64(-0x0.8000000000000p-1022) == -0x1.0
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; F64 NaN's
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; For NaN's this operation is specified as producing a value that is a NaN
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function %floor_is_nan_f64(f64) -> i32 {
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block0(v0: f64):
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v1 = floor v0
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v2 = fcmp ne v1, v1
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v3 = uextend.i32 v2
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return v3
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}
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; run: %floor_is_nan_f64(+NaN) == 1
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; run: %floor_is_nan_f64(-NaN) == 1
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; run: %floor_is_nan_f64(+NaN:0x0) == 1
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; run: %floor_is_nan_f64(+NaN:0x1) == 1
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; run: %floor_is_nan_f64(+NaN:0x4000000000001) == 1
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; run: %floor_is_nan_f64(-NaN:0x0) == 1
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; run: %floor_is_nan_f64(-NaN:0x1) == 1
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; run: %floor_is_nan_f64(-NaN:0x4000000000001) == 1
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; run: %floor_is_nan_f64(+sNaN:0x1) == 1
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; run: %floor_is_nan_f64(-sNaN:0x1) == 1
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; run: %floor_is_nan_f64(+sNaN:0x4000000000001) == 1
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; run: %floor_is_nan_f64(-sNaN:0x4000000000001) == 1
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