cdecc858b4
Add a RISC-V 64 (`riscv64`, RV64GC) backend. Co-authored-by: yuyang <756445638@qq.com> Co-authored-by: Chris Fallin <chris@cfallin.org> Co-authored-by: Afonso Bordado <afonsobordado@az8.co>
45 lines
1.1 KiB
Plaintext
45 lines
1.1 KiB
Plaintext
test run
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target aarch64
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target aarch64 has_lse
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target x86_64
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target s390x
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target riscv64 has_a
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; We can't test that these instructions are right regarding atomicity, but we can
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; test if they perform their operation correctly
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function %atomic_cas_i64(i64, i64, i64) -> i64 {
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ss0 = explicit_slot 8
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block0(v0: i64, v1: i64, v2: i64):
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stack_store.i64 v0, ss0
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v3 = stack_addr.i64 ss0
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v4 = atomic_cas.i64 v3, v1, v2
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v5 = stack_load.i64 ss0
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return v5
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}
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; run: %atomic_cas_i64(0, 0, 2) == 2
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; run: %atomic_cas_i64(1, 0, 2) == 1
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; run: %atomic_cas_i64(0, 1, 2) == 0
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; run: %atomic_cas_i64(0, 0, 0xC0FFEEEE_DECAFFFF) == 0xC0FFEEEE_DECAFFFF
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function %atomic_cas_i32(i32, i32, i32) -> i32 {
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ss0 = explicit_slot 4
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block0(v0: i32, v1: i32, v2: i32):
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stack_store.i32 v0, ss0
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v3 = stack_addr.i64 ss0
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v4 = atomic_cas.i32 v3, v1, v2
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v5 = stack_load.i32 ss0
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return v5
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}
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; run: %atomic_cas_i32(0, 0, 2) == 2
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; run: %atomic_cas_i32(1, 0, 2) == 1
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; run: %atomic_cas_i32(0, 1, 2) == 0
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; run: %atomic_cas_i32(0, 0, 0xC0FFEEEE) == 0xC0FFEEEE
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