48573b52b2
I hadn't realized before that the filetest backend for `test vcode` is doing essentially what `compile` is doing, but for new (`MachInst`) backends: it is just getting a disassembly and running it through filecheck. There's no reason not to reuse `test compile` for the AArch64 tests as well. This was motivated by the desire to have "this IR compiles successfully" tests work on both x86 and AArch64. It seems this should work fine by adding multiple `target` directives when a test case should be compile-tested on multiple architectures.
437 lines
8.4 KiB
Plaintext
437 lines
8.4 KiB
Plaintext
test compile
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target aarch64
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ROR, variable
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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function %f0(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = rotr.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: ror x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f1(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = rotr.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: ror w0, w0, w1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f2(i16, i16) -> i16 {
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block0(v0: i16, v1: i16):
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v2 = rotr.i16 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: uxth w0, w0
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; nextln: and w1, w1, #15
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; nextln: sub w2, w1, #16
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; nextln: sub w2, wzr, w2
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; nextln: lsr w1, w0, w1
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; nextln: lsl w0, w0, w2
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; nextln: orr w0, w0, w1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f3(i8, i8) -> i8 {
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block0(v0: i8, v1: i8):
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v2 = rotr.i8 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: uxtb w0, w0
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; nextln: and w1, w1, #7
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; nextln: sub w2, w1, #8
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; nextln: sub w2, wzr, w2
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; nextln: lsr w1, w0, w1
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; nextln: lsl w0, w0, w2
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; nextln: orr w0, w0, w1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ROL, variable
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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function %f4(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = rotl.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sub x1, xzr, x1
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; nextln: ror x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f5(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = rotl.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sub w1, wzr, w1
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; nextln: ror w0, w0, w1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f6(i16, i16) -> i16 {
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block0(v0: i16, v1: i16):
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v2 = rotl.i16 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: uxth w0, w0
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; nextln: sub w1, wzr, w1
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; nextln: and w1, w1, #15
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; nextln: sub w2, w1, #16
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; nextln: sub w2, wzr, w2
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; nextln: lsr w1, w0, w1
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; nextln: lsl w0, w0, w2
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; nextln: orr w0, w0, w1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f7(i8, i8) -> i8 {
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block0(v0: i8, v1: i8):
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v2 = rotl.i8 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: uxtb w0, w0
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; nextln: sub w1, wzr, w1
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; nextln: and w1, w1, #7
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; nextln: sub w2, w1, #8
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; nextln: sub w2, wzr, w2
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; nextln: lsr w1, w0, w1
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; nextln: lsl w0, w0, w2
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; nextln: orr w0, w0, w1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; LSR, variable
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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function %f8(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = ushr.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: lsr x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f9(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = ushr.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: lsr w0, w0, w1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f10(i16, i16) -> i16 {
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block0(v0: i16, v1: i16):
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v2 = ushr.i16 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: uxth w0, w0
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; nextln: lsr w0, w0, w1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f11(i8, i8) -> i8 {
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block0(v0: i8, v1: i8):
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v2 = ushr.i8 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: uxtb w0, w0
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; nextln: lsr w0, w0, w1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; LSL, variable
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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function %f12(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = ishl.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: lsl x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f13(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = ishl.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: lsl w0, w0, w1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f14(i16, i16) -> i16 {
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block0(v0: i16, v1: i16):
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v2 = ishl.i16 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: lsl w0, w0, w1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f15(i8, i8) -> i8 {
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block0(v0: i8, v1: i8):
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v2 = ishl.i8 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: lsl w0, w0, w1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ASR, variable
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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function %f16(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = sshr.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: asr x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f17(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = sshr.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: asr w0, w0, w1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f18(i16, i16) -> i16 {
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block0(v0: i16, v1: i16):
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v2 = sshr.i16 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sxth w0, w0
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; nextln: asr w0, w0, w1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f19(i8, i8) -> i8 {
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block0(v0: i8, v1: i8):
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v2 = sshr.i8 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sxtb w0, w0
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; nextln: asr w0, w0, w1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; immediate forms
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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function %f20(i64) -> i64 {
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block0(v0: i64):
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v1 = iconst.i32 17
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v2 = rotr.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: ror x0, x0, #17
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f21(i64) -> i64 {
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block0(v0: i64):
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v1 = iconst.i32 17
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v2 = rotl.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: ror x0, x0, #47
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f22(i32) -> i32 {
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block0(v0: i32):
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v1 = iconst.i32 17
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v2 = rotl.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: ror w0, w0, #15
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f23(i16) -> i16 {
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block0(v0: i16):
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v1 = iconst.i32 10
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v2 = rotl.i16 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: uxth w1, w0
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; nextln: lsr w0, w1, #6
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; nextln: lsl w1, w1, #10
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; nextln: orr w0, w1, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f24(i8) -> i8 {
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block0(v0: i8):
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v1 = iconst.i32 3
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v2 = rotl.i8 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: uxtb w1, w0
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; nextln: lsr w0, w1, #5
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; nextln: lsl w1, w1, #3
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; nextln: orr w0, w1, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f25(i64) -> i64 {
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block0(v0: i64):
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v1 = iconst.i32 17
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v2 = ushr.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: lsr x0, x0, #17
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f26(i64) -> i64 {
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block0(v0: i64):
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v1 = iconst.i32 17
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v2 = sshr.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: asr x0, x0, #17
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f27(i64) -> i64 {
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block0(v0: i64):
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v1 = iconst.i32 17
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v2 = ishl.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: lsl x0, x0, #17
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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