Jakob Stoklund Olesen 4e398164d2 Add icmp_imm encodings for RISC-V. ...

The ISA has icmp_imm slt/ult with 12-bit signed immediate operands.

2017-04-03 10:59:28 -07:00

..

arm32

Add a section about implementation limits.

2017-02-24 11:08:15 -08:00

arm64

Generate register class descriptors.

2017-01-20 14:23:06 -08:00

intel

Generate register class descriptors.

2017-01-20 14:23:06 -08:00

riscv

Add icmp_imm encodings for RISC-V.

2017-04-03 10:59:28 -07:00

__init__.py

Fixed for mypy 0.501.

2017-03-03 09:08:28 -08:00