4df6741a90
These map to single Intel instructions. The i64 to float conversions are not tested yet. The encoding tables can't yet differentiate instructions on a secondary type variable alone.
50 lines
1.6 KiB
Plaintext
50 lines
1.6 KiB
Plaintext
; Binary emission of 64-bit floating point code.
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test binemit
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set is_64bit
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isa intel has_sse2
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; The binary encodings can be verified with the command:
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;
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; sed -ne 's/^ *; asm: *//p' filetests/isa/intel/binary64-float.cton | llvm-mc -show-encoding -triple=x86_64
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;
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function %F32() {
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ebb0:
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[-,%r11] v0 = iconst.i32 1
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[-,%rsi] v1 = iconst.i32 2
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[-,%rax] v2 = iconst.i64 11
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[-,%r14] v3 = iconst.i64 12
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; asm: cvtsi2ssl %r11d, %xmm5
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[-,%xmm5] v10 = fcvt_from_sint.f32 v0 ; bin: f3 41 0f 2a eb
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; asm: cvtsi2ssl %esi, %xmm10
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[-,%xmm10] v11 = fcvt_from_sint.f32 v1 ; bin: f3 44 0f 2a d6
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; asm: cvtsi2ssq %rax, %xmm5
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[-,%xmm5] v12 = fcvt_from_sint.f32 v2 ; TODO: f3 48 0f 2a e8
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; asm: cvtsi2ssq %r14, %xmm10
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[-,%xmm10] v13 = fcvt_from_sint.f32 v3 ; TODO: f3 4d 0f 2a d6
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return
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}
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function %F64() {
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ebb0:
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[-,%r11] v0 = iconst.i32 1
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[-,%rsi] v1 = iconst.i32 2
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[-,%rax] v2 = iconst.i64 11
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[-,%r14] v3 = iconst.i64 12
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; asm: cvtsi2sdl %r11d, %xmm5
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[-,%xmm5] v10 = fcvt_from_sint.f64 v0 ; bin: f2 41 0f 2a eb
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; asm: cvtsi2sdl %esi, %xmm10
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[-,%xmm10] v11 = fcvt_from_sint.f64 v1 ; bin: f2 44 0f 2a d6
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; asm: cvtsi2sdq %rax, %xmm5
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[-,%xmm5] v12 = fcvt_from_sint.f64 v2 ; TODO: f2 48 0f 2a e8
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; asm: cvtsi2sdq %r14, %xmm10
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[-,%xmm10] v13 = fcvt_from_sint.f64 v3 ; TODO: f2 4d 0f 2a d6
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return
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}
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