4dce51096d
In existing MachInst backends, many instructions -- any that can trap or result in a relocation -- carry `SourceLoc` values in order to propagate the location-in-original-source to use to describe resulting traps or relocation errors. This is quite tedious, and also error-prone: it is likely that the necessary plumbing will be missed in some cases, and in any case, it's unnecessarily verbose. This PR factors out the `SourceLoc` handling so that it is tracked during emission as part of the `EmitState`, and plumbed through automatically by the machine-independent framework. Instruction emission code that directly emits trap or relocation records can query the current location as necessary. Then we only need to ensure that memory references and trap instructions, at their (one) emission point rather than their (many) lowering/generation points, are wired up correctly. This does have the side-effect that some loads and stores that do not correspond directly to user code's heap accesses will have unnecessary but harmless trap metadata. For example, the load that fetches a code offset from a jump table will have a 'heap out of bounds' trap record attached to it; but because it is bounds-checked, and will never actually trap if the lowering is correct, this should be harmless. The simplicity improvement here seemed more worthwhile to me than plumbing through a "corresponds to user-level load/store" bit, because the latter is a bit complex when we allow for op merging. Closes #2290: though it does not implement a full "metadata" scheme as described in that issue, this seems simpler overall.
1359 lines
40 KiB
Rust
1359 lines
40 KiB
Rust
//! This module defines 32-bit ARM specific machine instruction types.
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#![allow(dead_code)]
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use crate::binemit::CodeOffset;
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use crate::ir::types::{B1, B16, B32, B8, I16, I32, I8, IFLAGS};
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use crate::ir::{ExternalName, Opcode, TrapCode, Type};
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use crate::machinst::*;
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use crate::{settings, CodegenError, CodegenResult};
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use regalloc::{PrettyPrint, RealRegUniverse, Reg, RegClass, SpillSlot, VirtualReg, Writable};
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use regalloc::{RegUsageCollector, RegUsageMapper};
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use alloc::boxed::Box;
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use alloc::vec::Vec;
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use smallvec::{smallvec, SmallVec};
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use std::string::{String, ToString};
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mod args;
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pub use self::args::*;
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mod emit;
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pub use self::emit::*;
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mod regs;
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pub use self::regs::*;
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pub mod unwind;
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#[cfg(test)]
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mod emit_tests;
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//=============================================================================
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// Instructions (top level): definition
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/// An ALU operation. This can be paired with several instruction formats
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/// below (see `Inst`) in any combination.
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#[derive(Copy, Clone, Debug, PartialEq, Eq, Hash)]
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pub enum ALUOp {
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Add,
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Adds,
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Adc,
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Adcs,
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Qadd,
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Sub,
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Subs,
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Sbc,
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Sbcs,
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Rsb,
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Qsub,
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Mul,
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Smull,
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Umull,
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Udiv,
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Sdiv,
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And,
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Orr,
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Orn,
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Eor,
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Bic,
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Lsl,
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Lsr,
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Asr,
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Ror,
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}
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/// An ALU operation with one argument.
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#[derive(Copy, Clone, Debug, PartialEq, Eq, Hash)]
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pub enum ALUOp1 {
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Mvn,
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Mov,
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}
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/// An operation on the bits of a register.
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#[derive(Copy, Clone, Debug, PartialEq, Eq, Hash)]
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pub enum BitOp {
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Rbit,
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Rev,
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Clz,
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}
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/// Additional information for (direct) Call instructions, left out of line to lower the size of
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/// the Inst enum.
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#[derive(Clone, Debug)]
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pub struct CallInfo {
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pub dest: ExternalName,
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pub uses: Vec<Reg>,
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pub defs: Vec<Writable<Reg>>,
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pub opcode: Opcode,
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}
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/// Additional information for CallInd instructions, left out of line to lower the size of the Inst
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/// enum.
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#[derive(Clone, Debug)]
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pub struct CallIndInfo {
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pub rm: Reg,
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pub uses: Vec<Reg>,
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pub defs: Vec<Writable<Reg>>,
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pub opcode: Opcode,
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}
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/// Instruction formats.
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#[derive(Clone, Debug)]
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pub enum Inst {
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/// A no-op of zero size.
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Nop0,
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/// A no-op that is two bytes large.
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Nop2,
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/// An ALU operation with two register sources and one register destination.
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AluRRR {
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alu_op: ALUOp,
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rd: Writable<Reg>,
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rn: Reg,
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rm: Reg,
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},
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/// An ALU operation with two register sources, one of which can be optionally shifted
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/// and one register destination.
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AluRRRShift {
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alu_op: ALUOp,
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rd: Writable<Reg>,
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rn: Reg,
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rm: Reg,
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shift: Option<ShiftOpAndAmt>,
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},
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/// An ALU operation with one register source, which can be optionally shifted
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/// and one register destination.
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AluRRShift {
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alu_op: ALUOp1,
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rd: Writable<Reg>,
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rm: Reg,
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shift: Option<ShiftOpAndAmt>,
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},
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/// An ALU operation with two register sources and two register destinations.
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AluRRRR {
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alu_op: ALUOp,
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rd_hi: Writable<Reg>,
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rd_lo: Writable<Reg>,
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rn: Reg,
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rm: Reg,
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},
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/// An ALU operation with a register source and a 12-bit immediate source,
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/// and a register destination.
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AluRRImm12 {
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alu_op: ALUOp,
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rd: Writable<Reg>,
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rn: Reg,
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imm12: UImm12,
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},
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/// An ALU operation with a register source and a 8-bit immediate source,
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/// and a register destination.
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///
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/// In fact these instructions take a `modified immediate constant` operand,
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/// which is encoded as a 12-bit immediate. The only case used here
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/// is when high 4 bits of that 12-immediate are zeros.
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/// In this case operand is simple 8-bit immediate.
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/// For all possible operands see
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/// https://static.docs.arm.com/ddi0406/c/DDI0406C_C_arm_architecture_reference_manual.pdf#G10.4954509
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AluRRImm8 {
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alu_op: ALUOp,
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rd: Writable<Reg>,
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rn: Reg,
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imm8: UImm8,
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},
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/// An ALU operation with a 8-bit immediate and a register destination.
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/// See `AluRRImm8` description above.
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AluRImm8 {
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alu_op: ALUOp1,
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rd: Writable<Reg>,
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imm8: UImm8,
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},
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/// A bit operation with a register source and a register destination.
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BitOpRR {
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bit_op: BitOp,
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rd: Writable<Reg>,
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rm: Reg,
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},
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/// A mov instruction with a GPR source and a GPR destination.
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Mov {
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rd: Writable<Reg>,
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rm: Reg,
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},
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/// A move instruction with a 16-bit immediate source and a register destination.
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MovImm16 {
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rd: Writable<Reg>,
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imm16: u16,
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},
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/// A move top instruction, which writes 16-bit immediate to the top
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/// halfword of the destination register.
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Movt {
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rd: Writable<Reg>,
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imm16: u16,
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},
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/// A compare instruction with two register arguments.
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Cmp {
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rn: Reg,
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rm: Reg,
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},
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/// A compare instruction with a register operand and a 8-bit immediate operand.
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CmpImm8 {
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rn: Reg,
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imm8: u8,
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},
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/// A store instruction, which stores to memory 8, 16 or 32-bit operand.
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Store {
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rt: Reg,
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mem: AMode,
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bits: u8,
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},
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/// A load instruction, which loads from memory 8, 16 or 32-bit operand,
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/// which can be sign- or zero-extended.
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Load {
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rt: Writable<Reg>,
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mem: AMode,
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bits: u8,
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sign_extend: bool,
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},
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/// Load address referenced by `mem` into `rd`.
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LoadAddr {
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rd: Writable<Reg>,
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mem: AMode,
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},
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/// A sign- or zero-extend operation.
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Extend {
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rd: Writable<Reg>,
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rm: Reg,
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from_bits: u8,
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signed: bool,
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},
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// An If-Then instruction, which makes up to four instructions conditinal.
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It {
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cond: Cond,
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insts: Vec<CondInst>,
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},
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/// A push instuction, which stores registers to the stack and updates sp.
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Push {
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reg_list: Vec<Reg>,
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},
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/// A pop instuction, which load registers from the stack and updates sp.
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Pop {
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reg_list: Vec<Writable<Reg>>,
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},
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/// A machine call instruction.
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Call {
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info: Box<CallInfo>,
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},
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/// A machine indirect-call instruction.
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CallInd {
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info: Box<CallIndInfo>,
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},
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/// Load an inline symbol reference.
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LoadExtName {
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rt: Writable<Reg>,
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name: Box<ExternalName>,
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offset: i32,
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},
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/// A return instruction, which is encoded as `bx lr`.
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Ret,
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/// An unconditional branch.
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Jump {
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dest: BranchTarget,
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},
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/// A conditional branch.
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CondBr {
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taken: BranchTarget,
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not_taken: BranchTarget,
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cond: Cond,
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},
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/// An indirect branch through a register, augmented with set of all
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/// possible successors.
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IndirectBr {
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rm: Reg,
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targets: Vec<MachLabel>,
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},
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/// A conditional trap: execute a `udf` if the condition is true. This is
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/// one VCode instruction because it uses embedded control flow; it is
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/// logically a single-in, single-out region, but needs to appear as one
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/// unit to the register allocator.
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TrapIf {
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cond: Cond,
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trap_info: TrapCode,
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},
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/// An instruction guaranteed to always be undefined and to trigger an illegal instruction at
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/// runtime.
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Udf {
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trap_info: TrapCode,
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},
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/// A "breakpoint" instruction, used for e.g. traps and debug breakpoints.
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Bkpt,
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/// Marker, no-op in generated code: SP "virtual offset" is adjusted.
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VirtualSPOffsetAdj {
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offset: i64,
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},
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/// A placeholder instruction, generating no code, meaning that a function epilogue must be
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/// inserted there.
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EpiloguePlaceholder,
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}
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/// An instruction inside an it block.
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#[derive(Clone, Debug)]
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pub struct CondInst {
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inst: Inst,
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// In which case execute the instruction:
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// true => when it condition is met
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// false => otherwise.
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then: bool,
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}
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impl CondInst {
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pub fn new(inst: Inst, then: bool) -> Self {
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match inst {
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Inst::It { .. }
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| Inst::Ret { .. }
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| Inst::Jump { .. }
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| Inst::CondBr { .. }
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| Inst::TrapIf { .. }
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| Inst::EpiloguePlaceholder { .. }
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| Inst::LoadExtName { .. } => panic!("Instruction {:?} cannot occur in it block", inst),
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_ => Self { inst, then },
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}
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}
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}
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impl Inst {
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/// Create a move instruction.
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pub fn mov(to_reg: Writable<Reg>, from_reg: Reg) -> Inst {
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Inst::Mov {
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rd: to_reg,
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rm: from_reg,
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}
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}
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/// Create an instruction that loads a constant.
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pub fn load_constant(rd: Writable<Reg>, value: u32) -> SmallVec<[Inst; 4]> {
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let mut insts = smallvec![];
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let imm_lo = (value & 0xffff) as u16;
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let imm_hi = (value >> 16) as u16;
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if imm_lo != 0 || imm_hi == 0 {
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// imm_lo == 0 && imm_hi == 0 => we have to overwrite reg value with 0
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insts.push(Inst::MovImm16 { rd, imm16: imm_lo });
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}
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if imm_hi != 0 {
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insts.push(Inst::Movt { rd, imm16: imm_hi });
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}
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insts
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}
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/// Generic constructor for a load (zero-extending where appropriate).
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pub fn gen_load(into_reg: Writable<Reg>, mem: AMode, ty: Type) -> Inst {
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assert!(ty.bits() <= 32);
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// Load 8 bits for B1.
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let bits = std::cmp::max(ty.bits(), 8) as u8;
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Inst::Load {
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rt: into_reg,
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mem,
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bits,
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sign_extend: false,
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}
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}
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/// Generic constructor for a store.
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pub fn gen_store(from_reg: Reg, mem: AMode, ty: Type) -> Inst {
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assert!(ty.bits() <= 32);
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// Store 8 bits for B1.
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let bits = std::cmp::max(ty.bits(), 8) as u8;
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Inst::Store {
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rt: from_reg,
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mem,
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bits,
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}
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}
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}
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//=============================================================================
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// Instructions: get_regs
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fn memarg_regs(memarg: &AMode, collector: &mut RegUsageCollector) {
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match memarg {
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&AMode::RegReg(rn, rm, ..) => {
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collector.add_use(rn);
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collector.add_use(rm);
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}
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&AMode::RegOffset12(rn, ..) | &AMode::RegOffset(rn, _) => {
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collector.add_use(rn);
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}
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&AMode::SPOffset(..) | &AMode::NominalSPOffset(..) => {
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collector.add_use(sp_reg());
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}
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&AMode::FPOffset(..) => {
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collector.add_use(fp_reg());
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}
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&AMode::PCRel(_) => {}
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}
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}
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fn arm32_get_regs(inst: &Inst, collector: &mut RegUsageCollector) {
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match inst {
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&Inst::Nop0
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| &Inst::Nop2
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| &Inst::Ret
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| &Inst::VirtualSPOffsetAdj { .. }
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| &Inst::EpiloguePlaceholder
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| &Inst::Jump { .. }
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| &Inst::CondBr { .. }
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| &Inst::Bkpt
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| &Inst::Udf { .. }
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| &Inst::TrapIf { .. } => {}
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&Inst::AluRRR { rd, rn, rm, .. } => {
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collector.add_def(rd);
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collector.add_use(rn);
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collector.add_use(rm);
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}
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&Inst::AluRRRShift { rd, rn, rm, .. } => {
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collector.add_def(rd);
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collector.add_use(rn);
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collector.add_use(rm);
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}
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&Inst::AluRRShift { rd, rm, .. } => {
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collector.add_def(rd);
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collector.add_use(rm);
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}
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&Inst::AluRRRR {
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rd_hi,
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rd_lo,
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rn,
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rm,
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..
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} => {
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collector.add_def(rd_hi);
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collector.add_def(rd_lo);
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collector.add_use(rn);
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collector.add_use(rm);
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}
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&Inst::AluRRImm12 { rd, rn, .. } => {
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collector.add_def(rd);
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collector.add_use(rn);
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}
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&Inst::AluRRImm8 { rd, rn, .. } => {
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collector.add_def(rd);
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collector.add_use(rn);
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}
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&Inst::AluRImm8 { rd, .. } => {
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collector.add_def(rd);
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}
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&Inst::BitOpRR { rd, rm, .. } => {
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collector.add_def(rd);
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collector.add_use(rm);
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}
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&Inst::Mov { rd, rm, .. } => {
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collector.add_def(rd);
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collector.add_use(rm);
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}
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&Inst::MovImm16 { rd, .. } => {
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collector.add_def(rd);
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}
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&Inst::Movt { rd, .. } => {
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collector.add_def(rd);
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}
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&Inst::Cmp { rn, rm } => {
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collector.add_use(rn);
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collector.add_use(rm);
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}
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&Inst::CmpImm8 { rn, .. } => {
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collector.add_use(rn);
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}
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&Inst::Store { rt, ref mem, .. } => {
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collector.add_use(rt);
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memarg_regs(mem, collector);
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}
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&Inst::Load { rt, ref mem, .. } => {
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collector.add_def(rt);
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memarg_regs(mem, collector);
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}
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&Inst::LoadAddr { rd, mem: _ } => {
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collector.add_def(rd);
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}
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&Inst::Extend { rd, rm, .. } => {
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collector.add_def(rd);
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collector.add_use(rm);
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}
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&Inst::It { ref insts, .. } => {
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for inst in insts.iter() {
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arm32_get_regs(&inst.inst, collector);
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}
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}
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&Inst::Push { ref reg_list } => {
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for reg in reg_list {
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collector.add_use(*reg);
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}
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}
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|
&Inst::Pop { ref reg_list } => {
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for reg in reg_list {
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collector.add_def(*reg);
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}
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}
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|
&Inst::Call { ref info, .. } => {
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collector.add_uses(&*info.uses);
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collector.add_defs(&*info.defs);
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}
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&Inst::CallInd { ref info, .. } => {
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collector.add_uses(&*info.uses);
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collector.add_defs(&*info.defs);
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collector.add_use(info.rm);
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}
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&Inst::LoadExtName { rt, .. } => {
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collector.add_def(rt);
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}
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&Inst::IndirectBr { rm, .. } => {
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collector.add_use(rm);
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}
|
|
}
|
|
}
|
|
|
|
//=============================================================================
|
|
// Instructions: map_regs
|
|
|
|
fn arm32_map_regs<RUM: RegUsageMapper>(inst: &mut Inst, mapper: &RUM) {
|
|
fn map_use<RUM: RegUsageMapper>(m: &RUM, r: &mut Reg) {
|
|
if r.is_virtual() {
|
|
let new = m.get_use(r.to_virtual_reg()).unwrap().to_reg();
|
|
*r = new;
|
|
}
|
|
}
|
|
|
|
fn map_def<RUM: RegUsageMapper>(m: &RUM, r: &mut Writable<Reg>) {
|
|
if r.to_reg().is_virtual() {
|
|
let new = m.get_def(r.to_reg().to_virtual_reg()).unwrap().to_reg();
|
|
*r = Writable::from_reg(new);
|
|
}
|
|
}
|
|
|
|
fn map_mod<RUM: RegUsageMapper>(m: &RUM, r: &mut Writable<Reg>) {
|
|
if r.to_reg().is_virtual() {
|
|
let new = m.get_mod(r.to_reg().to_virtual_reg()).unwrap().to_reg();
|
|
*r = Writable::from_reg(new);
|
|
}
|
|
}
|
|
|
|
fn map_mem<RUM: RegUsageMapper>(m: &RUM, mem: &mut AMode) {
|
|
match mem {
|
|
&mut AMode::RegReg(ref mut rn, ref mut rm, ..) => {
|
|
map_use(m, rn);
|
|
map_use(m, rm);
|
|
}
|
|
&mut AMode::RegOffset12(ref mut rn, ..) | &mut AMode::RegOffset(ref mut rn, ..) => {
|
|
map_use(m, rn)
|
|
}
|
|
&mut AMode::SPOffset(..)
|
|
| &mut AMode::FPOffset(..)
|
|
| &mut AMode::NominalSPOffset(..)
|
|
| &mut AMode::PCRel(_) => {}
|
|
};
|
|
}
|
|
|
|
match inst {
|
|
&mut Inst::Nop0
|
|
| &mut Inst::Nop2
|
|
| &mut Inst::Ret
|
|
| &mut Inst::VirtualSPOffsetAdj { .. }
|
|
| &mut Inst::EpiloguePlaceholder
|
|
| &mut Inst::Jump { .. }
|
|
| &mut Inst::CondBr { .. }
|
|
| &mut Inst::Bkpt
|
|
| &mut Inst::Udf { .. }
|
|
| &mut Inst::TrapIf { .. } => {}
|
|
&mut Inst::AluRRR {
|
|
ref mut rd,
|
|
ref mut rn,
|
|
ref mut rm,
|
|
..
|
|
} => {
|
|
map_def(mapper, rd);
|
|
map_use(mapper, rn);
|
|
map_use(mapper, rm);
|
|
}
|
|
&mut Inst::AluRRRShift {
|
|
ref mut rd,
|
|
ref mut rn,
|
|
ref mut rm,
|
|
..
|
|
} => {
|
|
map_def(mapper, rd);
|
|
map_use(mapper, rn);
|
|
map_use(mapper, rm);
|
|
}
|
|
&mut Inst::AluRRShift {
|
|
ref mut rd,
|
|
ref mut rm,
|
|
..
|
|
} => {
|
|
map_def(mapper, rd);
|
|
map_use(mapper, rm);
|
|
}
|
|
&mut Inst::AluRRRR {
|
|
ref mut rd_hi,
|
|
ref mut rd_lo,
|
|
ref mut rn,
|
|
ref mut rm,
|
|
..
|
|
} => {
|
|
map_def(mapper, rd_hi);
|
|
map_def(mapper, rd_lo);
|
|
map_use(mapper, rn);
|
|
map_use(mapper, rm);
|
|
}
|
|
&mut Inst::AluRRImm12 {
|
|
ref mut rd,
|
|
ref mut rn,
|
|
..
|
|
} => {
|
|
map_def(mapper, rd);
|
|
map_use(mapper, rn);
|
|
}
|
|
&mut Inst::AluRRImm8 {
|
|
ref mut rd,
|
|
ref mut rn,
|
|
..
|
|
} => {
|
|
map_def(mapper, rd);
|
|
map_use(mapper, rn);
|
|
}
|
|
&mut Inst::AluRImm8 { ref mut rd, .. } => {
|
|
map_def(mapper, rd);
|
|
}
|
|
&mut Inst::BitOpRR {
|
|
ref mut rd,
|
|
ref mut rm,
|
|
..
|
|
} => {
|
|
map_def(mapper, rd);
|
|
map_use(mapper, rm);
|
|
}
|
|
&mut Inst::Mov {
|
|
ref mut rd,
|
|
ref mut rm,
|
|
..
|
|
} => {
|
|
map_def(mapper, rd);
|
|
map_use(mapper, rm);
|
|
}
|
|
&mut Inst::MovImm16 { ref mut rd, .. } => {
|
|
map_def(mapper, rd);
|
|
}
|
|
&mut Inst::Movt { ref mut rd, .. } => {
|
|
map_def(mapper, rd);
|
|
}
|
|
&mut Inst::Cmp {
|
|
ref mut rn,
|
|
ref mut rm,
|
|
} => {
|
|
map_use(mapper, rn);
|
|
map_use(mapper, rm);
|
|
}
|
|
&mut Inst::CmpImm8 { ref mut rn, .. } => {
|
|
map_use(mapper, rn);
|
|
}
|
|
&mut Inst::Store {
|
|
ref mut rt,
|
|
ref mut mem,
|
|
..
|
|
} => {
|
|
map_use(mapper, rt);
|
|
map_mem(mapper, mem);
|
|
}
|
|
&mut Inst::Load {
|
|
ref mut rt,
|
|
ref mut mem,
|
|
..
|
|
} => {
|
|
map_def(mapper, rt);
|
|
map_mem(mapper, mem);
|
|
}
|
|
&mut Inst::LoadAddr {
|
|
ref mut rd,
|
|
ref mut mem,
|
|
} => {
|
|
map_def(mapper, rd);
|
|
map_mem(mapper, mem);
|
|
}
|
|
&mut Inst::Extend {
|
|
ref mut rd,
|
|
ref mut rm,
|
|
..
|
|
} => {
|
|
map_def(mapper, rd);
|
|
map_use(mapper, rm);
|
|
}
|
|
&mut Inst::It { ref mut insts, .. } => {
|
|
for inst in insts.iter_mut() {
|
|
arm32_map_regs(&mut inst.inst, mapper);
|
|
}
|
|
}
|
|
&mut Inst::Push { ref mut reg_list } => {
|
|
for reg in reg_list {
|
|
map_use(mapper, reg);
|
|
}
|
|
}
|
|
&mut Inst::Pop { ref mut reg_list } => {
|
|
for reg in reg_list {
|
|
map_def(mapper, reg);
|
|
}
|
|
}
|
|
&mut Inst::Call { ref mut info } => {
|
|
for r in info.uses.iter_mut() {
|
|
map_use(mapper, r);
|
|
}
|
|
for r in info.defs.iter_mut() {
|
|
map_def(mapper, r);
|
|
}
|
|
}
|
|
&mut Inst::CallInd { ref mut info, .. } => {
|
|
for r in info.uses.iter_mut() {
|
|
map_use(mapper, r);
|
|
}
|
|
for r in info.defs.iter_mut() {
|
|
map_def(mapper, r);
|
|
}
|
|
map_use(mapper, &mut info.rm);
|
|
}
|
|
&mut Inst::LoadExtName { ref mut rt, .. } => {
|
|
map_def(mapper, rt);
|
|
}
|
|
&mut Inst::IndirectBr { ref mut rm, .. } => {
|
|
map_use(mapper, rm);
|
|
}
|
|
}
|
|
}
|
|
|
|
//=============================================================================
|
|
// Instructions: misc functions and external interface
|
|
|
|
impl MachInst for Inst {
|
|
type LabelUse = LabelUse;
|
|
|
|
fn get_regs(&self, collector: &mut RegUsageCollector) {
|
|
arm32_get_regs(self, collector)
|
|
}
|
|
|
|
fn map_regs<RUM: RegUsageMapper>(&mut self, mapper: &RUM) {
|
|
arm32_map_regs(self, mapper);
|
|
}
|
|
|
|
fn is_move(&self) -> Option<(Writable<Reg>, Reg)> {
|
|
match self {
|
|
&Inst::Mov { rd, rm } => Some((rd, rm)),
|
|
_ => None,
|
|
}
|
|
}
|
|
|
|
fn is_epilogue_placeholder(&self) -> bool {
|
|
if let Inst::EpiloguePlaceholder = self {
|
|
true
|
|
} else {
|
|
false
|
|
}
|
|
}
|
|
|
|
fn is_term<'a>(&'a self) -> MachTerminator<'a> {
|
|
match self {
|
|
&Inst::Ret | &Inst::EpiloguePlaceholder => MachTerminator::Ret,
|
|
&Inst::Jump { dest } => MachTerminator::Uncond(dest.as_label().unwrap()),
|
|
&Inst::CondBr {
|
|
taken, not_taken, ..
|
|
} => MachTerminator::Cond(taken.as_label().unwrap(), not_taken.as_label().unwrap()),
|
|
&Inst::IndirectBr { ref targets, .. } => MachTerminator::Indirect(&targets[..]),
|
|
_ => MachTerminator::None,
|
|
}
|
|
}
|
|
|
|
fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, _ty: Type) -> Inst {
|
|
assert_eq!(from_reg.get_class(), RegClass::I32);
|
|
assert_eq!(to_reg.to_reg().get_class(), from_reg.get_class());
|
|
|
|
Inst::mov(to_reg, from_reg)
|
|
}
|
|
|
|
fn gen_constant<F: FnMut(RegClass, Type) -> Writable<Reg>>(
|
|
to_reg: Writable<Reg>,
|
|
value: u64,
|
|
ty: Type,
|
|
_alloc_tmp: F,
|
|
) -> SmallVec<[Inst; 4]> {
|
|
match ty {
|
|
B1 | I8 | B8 | I16 | B16 | I32 | B32 => {
|
|
let v: i64 = value as i64;
|
|
|
|
if v >= (1 << 32) || v < -(1 << 32) {
|
|
panic!("Cannot load constant value {}", value)
|
|
}
|
|
Inst::load_constant(to_reg, value as u32)
|
|
}
|
|
_ => unimplemented!(),
|
|
}
|
|
}
|
|
|
|
fn gen_zero_len_nop() -> Inst {
|
|
Inst::Nop0
|
|
}
|
|
|
|
fn gen_nop(preferred_size: usize) -> Inst {
|
|
assert!(preferred_size >= 2);
|
|
Inst::Nop2
|
|
}
|
|
|
|
fn maybe_direct_reload(&self, _reg: VirtualReg, _slot: SpillSlot) -> Option<Inst> {
|
|
None
|
|
}
|
|
|
|
fn rc_for_type(ty: Type) -> CodegenResult<RegClass> {
|
|
match ty {
|
|
I8 | I16 | I32 | B1 | B8 | B16 | B32 => Ok(RegClass::I32),
|
|
IFLAGS => Ok(RegClass::I32),
|
|
_ => Err(CodegenError::Unsupported(format!(
|
|
"Unexpected SSA-value type: {}",
|
|
ty
|
|
))),
|
|
}
|
|
}
|
|
|
|
fn gen_jump(target: MachLabel) -> Inst {
|
|
Inst::Jump {
|
|
dest: BranchTarget::Label(target),
|
|
}
|
|
}
|
|
|
|
fn reg_universe(_flags: &settings::Flags) -> RealRegUniverse {
|
|
create_reg_universe()
|
|
}
|
|
|
|
fn worst_case_size() -> CodeOffset {
|
|
// It inst with four 32-bit instructions
|
|
2 + 4 * 4
|
|
}
|
|
|
|
fn ref_type_regclass(_: &settings::Flags) -> RegClass {
|
|
RegClass::I32
|
|
}
|
|
}
|
|
|
|
//=============================================================================
|
|
// Pretty-printing of instructions.
|
|
|
|
fn mem_finalize_for_show(
|
|
mem: &AMode,
|
|
mb_rru: Option<&RealRegUniverse>,
|
|
state: &EmitState,
|
|
) -> (String, AMode) {
|
|
let (mem_insts, mem) = mem_finalize(mem, state);
|
|
let mut mem_str = mem_insts
|
|
.into_iter()
|
|
.map(|inst| inst.show_rru(mb_rru))
|
|
.collect::<Vec<_>>()
|
|
.join(" ; ");
|
|
if !mem_str.is_empty() {
|
|
mem_str += " ; ";
|
|
}
|
|
|
|
(mem_str, mem)
|
|
}
|
|
|
|
impl PrettyPrint for Inst {
|
|
fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String {
|
|
self.pretty_print(mb_rru, &mut EmitState::default())
|
|
}
|
|
}
|
|
|
|
impl Inst {
|
|
fn print_with_state(&self, mb_rru: Option<&RealRegUniverse>, state: &mut EmitState) -> String {
|
|
fn op_name(alu_op: ALUOp) -> &'static str {
|
|
match alu_op {
|
|
ALUOp::Add => "add",
|
|
ALUOp::Adds => "adds",
|
|
ALUOp::Adc => "adc",
|
|
ALUOp::Adcs => "adcs",
|
|
ALUOp::Qadd => "qadd",
|
|
ALUOp::Sub => "sub",
|
|
ALUOp::Subs => "subs",
|
|
ALUOp::Sbc => "sbc",
|
|
ALUOp::Sbcs => "sbcs",
|
|
ALUOp::Rsb => "rsb",
|
|
ALUOp::Qsub => "qsub",
|
|
ALUOp::Mul => "mul",
|
|
ALUOp::Smull => "smull",
|
|
ALUOp::Umull => "umull",
|
|
ALUOp::Udiv => "udiv",
|
|
ALUOp::Sdiv => "sdiv",
|
|
ALUOp::And => "and",
|
|
ALUOp::Orr => "orr",
|
|
ALUOp::Orn => "orn",
|
|
ALUOp::Eor => "eor",
|
|
ALUOp::Bic => "bic",
|
|
ALUOp::Lsl => "lsl",
|
|
ALUOp::Lsr => "lsr",
|
|
ALUOp::Asr => "asr",
|
|
ALUOp::Ror => "ror",
|
|
}
|
|
}
|
|
|
|
fn reg_shift_str(
|
|
shift: &Option<ShiftOpAndAmt>,
|
|
mb_rru: Option<&RealRegUniverse>,
|
|
) -> String {
|
|
if let Some(ref shift) = shift {
|
|
format!(", {}", shift.show_rru(mb_rru))
|
|
} else {
|
|
"".to_string()
|
|
}
|
|
}
|
|
|
|
match self {
|
|
&Inst::Nop0 => "nop-zero-len".to_string(),
|
|
&Inst::Nop2 => "nop".to_string(),
|
|
&Inst::AluRRR { alu_op, rd, rn, rm } => {
|
|
let op = op_name(alu_op);
|
|
let rd = rd.show_rru(mb_rru);
|
|
let rn = rn.show_rru(mb_rru);
|
|
let rm = rm.show_rru(mb_rru);
|
|
format!("{} {}, {}, {}", op, rd, rn, rm)
|
|
}
|
|
&Inst::AluRRRShift {
|
|
alu_op,
|
|
rd,
|
|
rn,
|
|
rm,
|
|
ref shift,
|
|
} => {
|
|
let op = op_name(alu_op);
|
|
let rd = rd.show_rru(mb_rru);
|
|
let rn = rn.show_rru(mb_rru);
|
|
let rm = rm.show_rru(mb_rru);
|
|
let shift = reg_shift_str(shift, mb_rru);
|
|
format!("{} {}, {}, {}{}", op, rd, rn, rm, shift)
|
|
}
|
|
&Inst::AluRRShift {
|
|
alu_op,
|
|
rd,
|
|
rm,
|
|
ref shift,
|
|
} => {
|
|
let op = match alu_op {
|
|
ALUOp1::Mvn => "mvn",
|
|
ALUOp1::Mov => "mov",
|
|
};
|
|
let rd = rd.show_rru(mb_rru);
|
|
let rm = rm.show_rru(mb_rru);
|
|
let shift = reg_shift_str(shift, mb_rru);
|
|
format!("{} {}, {}{}", op, rd, rm, shift)
|
|
}
|
|
&Inst::AluRRRR {
|
|
alu_op,
|
|
rd_hi,
|
|
rd_lo,
|
|
rn,
|
|
rm,
|
|
} => {
|
|
let op = op_name(alu_op);
|
|
let rd_hi = rd_hi.show_rru(mb_rru);
|
|
let rd_lo = rd_lo.show_rru(mb_rru);
|
|
let rn = rn.show_rru(mb_rru);
|
|
let rm = rm.show_rru(mb_rru);
|
|
format!("{} {}, {}, {}, {}", op, rd_lo, rd_hi, rn, rm)
|
|
}
|
|
&Inst::AluRRImm12 {
|
|
alu_op,
|
|
rd,
|
|
rn,
|
|
imm12,
|
|
} => {
|
|
let op = op_name(alu_op);
|
|
let rd = rd.show_rru(mb_rru);
|
|
let rn = rn.show_rru(mb_rru);
|
|
let imm = imm12.show_rru(mb_rru);
|
|
format!("{} {}, {}, {}", op, rd, rn, imm)
|
|
}
|
|
&Inst::AluRRImm8 {
|
|
alu_op,
|
|
rd,
|
|
rn,
|
|
imm8,
|
|
} => {
|
|
let op = op_name(alu_op);
|
|
let rd = rd.show_rru(mb_rru);
|
|
let rn = rn.show_rru(mb_rru);
|
|
let imm = imm8.show_rru(mb_rru);
|
|
format!("{} {}, {}, {}", op, rd, rn, imm)
|
|
}
|
|
&Inst::AluRImm8 { alu_op, rd, imm8 } => {
|
|
let op = match alu_op {
|
|
ALUOp1::Mvn => "mvn",
|
|
ALUOp1::Mov => "mov",
|
|
};
|
|
let rd = rd.show_rru(mb_rru);
|
|
let imm = imm8.show_rru(mb_rru);
|
|
format!("{} {}, {}", op, rd, imm)
|
|
}
|
|
&Inst::BitOpRR { bit_op, rd, rm } => {
|
|
let op = match bit_op {
|
|
BitOp::Rbit => "rbit",
|
|
BitOp::Rev => "rev",
|
|
BitOp::Clz => "clz",
|
|
};
|
|
let rd = rd.show_rru(mb_rru);
|
|
let rm = rm.show_rru(mb_rru);
|
|
format!("{} {}, {}", op, rd, rm)
|
|
}
|
|
&Inst::Mov { rd, rm } => {
|
|
let rd = rd.show_rru(mb_rru);
|
|
let rm = rm.show_rru(mb_rru);
|
|
format!("mov {}, {}", rd, rm)
|
|
}
|
|
&Inst::MovImm16 { rd, imm16 } => {
|
|
let rd = rd.show_rru(mb_rru);
|
|
format!("mov {}, #{}", rd, imm16)
|
|
}
|
|
&Inst::Movt { rd, imm16 } => {
|
|
let rd = rd.show_rru(mb_rru);
|
|
format!("movt {}, #{}", rd, imm16)
|
|
}
|
|
&Inst::Cmp { rn, rm } => {
|
|
let rn = rn.show_rru(mb_rru);
|
|
let rm = rm.show_rru(mb_rru);
|
|
format!("cmp {}, {}", rn, rm)
|
|
}
|
|
&Inst::CmpImm8 { rn, imm8 } => {
|
|
let rn = rn.show_rru(mb_rru);
|
|
format!("cmp {}, #{}", rn, imm8)
|
|
}
|
|
&Inst::Store {
|
|
rt, ref mem, bits, ..
|
|
} => {
|
|
let op = match bits {
|
|
32 => "str",
|
|
16 => "strh",
|
|
8 => "strb",
|
|
_ => panic!("Invalid bit amount {}", bits),
|
|
};
|
|
let rt = rt.show_rru(mb_rru);
|
|
let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru, state);
|
|
let mem = mem.show_rru(mb_rru);
|
|
format!("{}{} {}, {}", mem_str, op, rt, mem)
|
|
}
|
|
&Inst::Load {
|
|
rt,
|
|
ref mem,
|
|
bits,
|
|
sign_extend,
|
|
..
|
|
} => {
|
|
let op = match (bits, sign_extend) {
|
|
(32, _) => "ldr",
|
|
(16, true) => "ldrsh",
|
|
(16, false) => "ldrh",
|
|
(8, true) => "ldrsb",
|
|
(8, false) => "ldrb",
|
|
(_, _) => panic!("Invalid bit amount {}", bits),
|
|
};
|
|
let rt = rt.show_rru(mb_rru);
|
|
let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru, state);
|
|
let mem = mem.show_rru(mb_rru);
|
|
format!("{}{} {}, {}", mem_str, op, rt, mem)
|
|
}
|
|
&Inst::LoadAddr { rd, ref mem } => {
|
|
let mut ret = String::new();
|
|
let (mem_insts, mem) = mem_finalize(mem, state);
|
|
for inst in mem_insts.into_iter() {
|
|
ret.push_str(&inst.show_rru(mb_rru));
|
|
}
|
|
let inst = match mem {
|
|
AMode::RegReg(rn, rm, shift) => {
|
|
let shift = u32::from(shift);
|
|
let shift_amt = ShiftOpShiftImm::maybe_from_shift(shift).unwrap();
|
|
let shift = ShiftOpAndAmt::new(ShiftOp::LSL, shift_amt);
|
|
Inst::AluRRRShift {
|
|
alu_op: ALUOp::Add,
|
|
rd,
|
|
rn,
|
|
rm,
|
|
shift: Some(shift),
|
|
}
|
|
}
|
|
AMode::RegOffset12(reg, imm12) => Inst::AluRRImm12 {
|
|
alu_op: ALUOp::Add,
|
|
rd,
|
|
rn: reg,
|
|
imm12,
|
|
},
|
|
_ => unreachable!(),
|
|
};
|
|
ret.push_str(&inst.show_rru(mb_rru));
|
|
ret
|
|
}
|
|
&Inst::Extend {
|
|
rd,
|
|
rm,
|
|
from_bits,
|
|
signed,
|
|
} => {
|
|
let op = match (from_bits, signed) {
|
|
(16, true) => "sxth",
|
|
(16, false) => "uxth",
|
|
(8, true) => "sxtb",
|
|
(8, false) => "uxtb",
|
|
_ => panic!("Unsupported extend case: {:?}", self),
|
|
};
|
|
let rd = rd.show_rru(mb_rru);
|
|
let rm = rm.show_rru(mb_rru);
|
|
format!("{} {}, {}", op, rd, rm)
|
|
}
|
|
&Inst::It { cond, ref insts } => {
|
|
let te: String = insts
|
|
.iter()
|
|
.skip(1)
|
|
.map(|i| if i.then { "t" } else { "e" })
|
|
.collect();
|
|
let cond = cond.show_rru(mb_rru);
|
|
let mut ret = format!("it{} {}", te, cond);
|
|
for inst in insts.into_iter() {
|
|
ret.push_str(" ; ");
|
|
ret.push_str(&inst.inst.show_rru(mb_rru));
|
|
}
|
|
ret
|
|
}
|
|
&Inst::Push { ref reg_list } => {
|
|
assert!(!reg_list.is_empty());
|
|
let first_reg = reg_list[0].show_rru(mb_rru);
|
|
let regs: String = reg_list
|
|
.iter()
|
|
.skip(1)
|
|
.map(|r| [",", &r.show_rru(mb_rru)].join(" "))
|
|
.collect();
|
|
format!("push {{{}{}}}", first_reg, regs)
|
|
}
|
|
&Inst::Pop { ref reg_list } => {
|
|
assert!(!reg_list.is_empty());
|
|
let first_reg = reg_list[0].show_rru(mb_rru);
|
|
let regs: String = reg_list
|
|
.iter()
|
|
.skip(1)
|
|
.map(|r| [",", &r.show_rru(mb_rru)].join(" "))
|
|
.collect();
|
|
format!("pop {{{}{}}}", first_reg, regs)
|
|
}
|
|
&Inst::Call { .. } => format!("bl 0"),
|
|
&Inst::CallInd { ref info, .. } => {
|
|
let rm = info.rm.show_rru(mb_rru);
|
|
format!("blx {}", rm)
|
|
}
|
|
&Inst::LoadExtName {
|
|
rt,
|
|
ref name,
|
|
offset,
|
|
} => {
|
|
let rt = rt.show_rru(mb_rru);
|
|
format!("ldr {}, [pc, #4] ; b 4 ; data {:?} + {}", rt, name, offset)
|
|
}
|
|
&Inst::Ret => "bx lr".to_string(),
|
|
&Inst::VirtualSPOffsetAdj { offset } => format!("virtual_sp_offset_adjust {}", offset),
|
|
&Inst::EpiloguePlaceholder => "epilogue placeholder".to_string(),
|
|
&Inst::Jump { ref dest } => {
|
|
let dest = dest.show_rru(mb_rru);
|
|
format!("b {}", dest)
|
|
}
|
|
&Inst::CondBr {
|
|
ref taken,
|
|
ref not_taken,
|
|
ref cond,
|
|
} => {
|
|
let taken = taken.show_rru(mb_rru);
|
|
let not_taken = not_taken.show_rru(mb_rru);
|
|
let c = cond.show_rru(mb_rru);
|
|
format!("b{} {} ; b {}", c, taken, not_taken)
|
|
}
|
|
&Inst::IndirectBr { rm, .. } => {
|
|
let rm = rm.show_rru(mb_rru);
|
|
format!("bx {}", rm)
|
|
}
|
|
&Inst::Udf { .. } => "udf #0".to_string(),
|
|
&Inst::Bkpt => "bkpt #0".to_string(),
|
|
&Inst::TrapIf { cond, .. } => {
|
|
let c = cond.invert().show_rru(mb_rru);
|
|
format!("b{} 2 ; udf #0", c)
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
//=============================================================================
|
|
// Label fixups and jump veneers.
|
|
|
|
/// Different forms of label references for different instruction formats.
|
|
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
|
pub enum LabelUse {
|
|
/// 20-bit branch offset used by 32-bit conditional jumps.
|
|
Branch20,
|
|
|
|
/// 24-bit branch offset used by 32-bit uncoditional jump instruction.
|
|
Branch24,
|
|
}
|
|
|
|
impl MachInstLabelUse for LabelUse {
|
|
/// Alignment for veneer code. Every instruction must be 4-byte-aligned.
|
|
const ALIGN: CodeOffset = 2;
|
|
|
|
// Branches range:
|
|
// 20-bit sign-extended immediate gives us range [-(2^19), 2^19 - 1].
|
|
// Left-shifted by 1 => [-(2^20), 2^20 - 2].
|
|
// PC is start of this instruction + 4 bytes => [-(2^20) + 4, 2^20 + 2].
|
|
// Likewise for Branch24.
|
|
|
|
/// Maximum PC-relative range (positive), inclusive.
|
|
fn max_pos_range(self) -> CodeOffset {
|
|
match self {
|
|
LabelUse::Branch20 => (1 << 20) + 2,
|
|
LabelUse::Branch24 => (1 << 24) + 2,
|
|
}
|
|
}
|
|
|
|
/// Maximum PC-relative range (negative).
|
|
fn max_neg_range(self) -> CodeOffset {
|
|
match self {
|
|
LabelUse::Branch20 => (1 << 20) - 4,
|
|
LabelUse::Branch24 => (1 << 24) - 4,
|
|
}
|
|
}
|
|
|
|
/// Size of window into code needed to do the patch.
|
|
fn patch_size(self) -> CodeOffset {
|
|
4
|
|
}
|
|
|
|
/// Perform the patch.
|
|
fn patch(self, buffer: &mut [u8], use_offset: CodeOffset, label_offset: CodeOffset) {
|
|
let off = (label_offset as i64) - (use_offset as i64);
|
|
debug_assert!(off <= self.max_pos_range() as i64);
|
|
debug_assert!(off >= -(self.max_neg_range() as i64));
|
|
let off = off - 4;
|
|
match self {
|
|
LabelUse::Branch20 => {
|
|
let off = off as u32 >> 1;
|
|
let imm11 = (off & 0x7ff) as u16;
|
|
let imm6 = ((off >> 11) & 0x3f) as u16;
|
|
let j1 = ((off >> 17) & 0x1) as u16;
|
|
let j2 = ((off >> 18) & 0x1) as u16;
|
|
let s = ((off >> 19) & 0x1) as u16;
|
|
let insn_fst = u16::from_le_bytes([buffer[0], buffer[1]]);
|
|
let insn_fst = (insn_fst & !0x43f) | imm6 | (s << 10);
|
|
let insn_snd = u16::from_le_bytes([buffer[2], buffer[3]]);
|
|
let insn_snd = (insn_snd & !0x2fff) | imm11 | (j2 << 11) | (j1 << 13);
|
|
buffer[0..2].clone_from_slice(&u16::to_le_bytes(insn_fst));
|
|
buffer[2..4].clone_from_slice(&u16::to_le_bytes(insn_snd));
|
|
}
|
|
LabelUse::Branch24 => {
|
|
let off = off as u32 >> 1;
|
|
let imm11 = (off & 0x7ff) as u16;
|
|
let imm10 = ((off >> 11) & 0x3ff) as u16;
|
|
let s = ((off >> 23) & 0x1) as u16;
|
|
let j1 = (((off >> 22) & 0x1) as u16 ^ s) ^ 0x1;
|
|
let j2 = (((off >> 21) & 0x1) as u16 ^ s) ^ 0x1;
|
|
let insn_fst = u16::from_le_bytes([buffer[0], buffer[1]]);
|
|
let insn_fst = (insn_fst & !0x07ff) | imm10 | (s << 10);
|
|
let insn_snd = u16::from_le_bytes([buffer[2], buffer[3]]);
|
|
let insn_snd = (insn_snd & !0x2fff) | imm11 | (j2 << 11) | (j1 << 13);
|
|
buffer[0..2].clone_from_slice(&u16::to_le_bytes(insn_fst));
|
|
buffer[2..4].clone_from_slice(&u16::to_le_bytes(insn_snd));
|
|
}
|
|
}
|
|
}
|
|
|
|
fn supports_veneer(self) -> bool {
|
|
false
|
|
}
|
|
|
|
fn veneer_size(self) -> CodeOffset {
|
|
0
|
|
}
|
|
|
|
fn generate_veneer(
|
|
self,
|
|
_buffer: &mut [u8],
|
|
_veneer_offset: CodeOffset,
|
|
) -> (CodeOffset, LabelUse) {
|
|
panic!("Veneer not supported yet.")
|
|
}
|
|
}
|
|
|
|
#[cfg(test)]
|
|
mod tests {
|
|
use super::*;
|
|
|
|
#[test]
|
|
fn patch_branch20() {
|
|
let label_use = LabelUse::Branch20;
|
|
let mut buffer = 0x8000_f000_u32.to_le_bytes(); // beq
|
|
let use_offset: CodeOffset = 0;
|
|
let label_offset: CodeOffset = label_use.max_pos_range();
|
|
label_use.patch(&mut buffer, use_offset, label_offset);
|
|
assert_eq!(u16::from_le_bytes([buffer[0], buffer[1]]), 0xf03f);
|
|
assert_eq!(u16::from_le_bytes([buffer[2], buffer[3]]), 0xafff);
|
|
|
|
let mut buffer = 0x8000_f000_u32.to_le_bytes(); // beq
|
|
let use_offset = label_use.max_neg_range();
|
|
let label_offset: CodeOffset = 0;
|
|
label_use.patch(&mut buffer, use_offset, label_offset);
|
|
assert_eq!(u16::from_le_bytes([buffer[0], buffer[1]]), 0xf400);
|
|
assert_eq!(u16::from_le_bytes([buffer[2], buffer[3]]), 0x8000);
|
|
}
|
|
|
|
#[test]
|
|
fn patch_branch24() {
|
|
let label_use = LabelUse::Branch24;
|
|
let mut buffer = 0x9000_f000_u32.to_le_bytes(); // b
|
|
let use_offset: CodeOffset = 0;
|
|
let label_offset: CodeOffset = label_use.max_pos_range();
|
|
label_use.patch(&mut buffer, use_offset, label_offset);
|
|
assert_eq!(u16::from_le_bytes([buffer[0], buffer[1]]), 0xf3ff);
|
|
assert_eq!(u16::from_le_bytes([buffer[2], buffer[3]]), 0x97ff);
|
|
|
|
let mut buffer = 0x9000_f000_u32.to_le_bytes(); // b
|
|
let use_offset = label_use.max_neg_range();
|
|
let label_offset: CodeOffset = 0;
|
|
label_use.patch(&mut buffer, use_offset, label_offset);
|
|
assert_eq!(u16::from_le_bytes([buffer[0], buffer[1]]), 0xf400);
|
|
assert_eq!(u16::from_le_bytes([buffer[2], buffer[3]]), 0x9000);
|
|
}
|
|
}
|