4ca9e82bd1
Adds Bswap to the Cranelift IR. Implements the Bswap instruction in the x64 and aarch64 codegen backends. Cranelift users can now: ``` builder.ins().bswap(value) ``` to get a native byteswap instruction. * x64: implements the 32- and 64-bit bswap instruction, following the pattern set by similar unary instrutions (Neg and Not) - it only operates on a dst register, but is parameterized with both a src and dst which are expected to be the same register. As x64 bswap instruction is only for 32- or 64-bit registers, the 16-bit swap is implemented as a rotate left by 8. Updated x64 RexFlags type to support emitting for single-operand instructions like bswap * aarch64: Bswap gets emitted as aarch64 rev16, rev32, or rev64 instruction as appropriate. * s390x: Bswap was already supported in backend, just had to add a bit of plumbing * For completeness, added bswap to the interpreter as well. * added filetests and runtests for each ISA * added bswap to fuzzgen, thanks to afonso360 for the code there * 128-bit swaps are not yet implemented, that can be done later
35 lines
446 B
Plaintext
35 lines
446 B
Plaintext
test compile precise-output
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target s390x
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function %bswap_i64(i64) -> i64 {
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block0(v0: i64):
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v1 = bswap v0
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return v1
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}
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; block0:
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; lrvgr %r2, %r2
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; br %r14
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function %bswap_i32(i32) -> i32 {
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block0(v0: i32):
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v1 = bswap v0
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return v1
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}
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; block0:
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; lrvr %r2, %r2
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; br %r14
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function %bswap_i16(i16) -> i16 {
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block0(v0: i16):
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v1 = bswap v0
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return v1
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}
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; block0:
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; lrvr %r5, %r2
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; srlk %r2, %r5, 16
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; br %r14
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