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wasmtime/cranelift/codegen
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Damian Heaton 47a67d752b Split Fmla and Bsl out into new VecRRRMod op (#4638) 
Separates the following opcodes for AArch64 into a separate `VecALUModOp` enum,
which is emitted via the `VecRRRMod` instruction. This separates vector ALU
instructions which modify a register from instructions which write to a new register:
- `Bsl`
- `Fmla`

Addresses [a discussion](https://github.com/bytecodealliance/wasmtime/pull/4608#discussion_r937975581) in #4608.

Copyright (c) 2022 Arm Limited
2022-08-08 11:33:13 -07:00
..
benches
Fix cranelift-codegen benches
2021-10-10 14:19:08 +02:00
meta
Bump Wasmtime to 0.41.0 (#4620)
2022-08-04 20:02:19 -05:00
shared
Bump Wasmtime to 0.41.0 (#4620)
2022-08-04 20:02:19 -05:00
src
Split Fmla and Bsl out into new VecRRRMod op (#4638)
2022-08-08 11:33:13 -07:00
build.rs
[RFC] Dynamic Vector Support (#4200)
2022-07-07 12:54:39 -07:00
Cargo.toml
Bump Wasmtime to 0.41.0 (#4620)
2022-08-04 20:02:19 -05:00
LICENSE
moved crates in lib/ to src/, renamed crates, modified some files' text (#660)
2019-01-28 15:56:54 -08:00
README.md
moved crates in lib/ to src/, renamed crates, modified some files' text (#660)
2019-01-28 15:56:54 -08:00

README.md

This crate contains the core Cranelift code generator. It translates code from an intermediate representation into executable machine code.