13b0046ed7
This affects the comparison instructions which now read "icmp ult a, b". This mimics LLVM's style and makes it simpler to add instruction flags in the future, such as "load v1" -> "load aligned v1". These enumerated operands and flags feel like opcode modifiers rather than value operands, so displaying them differently makes sense. Value and numeric operands are still comma separated.
126 lines
4.2 KiB
Plaintext
126 lines
4.2 KiB
Plaintext
; Binary emission of 32-bit code.
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test binemit
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isa riscv
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function RV32I() {
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ebb0:
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[-,%x10] v1 = iconst.i32 1
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[-,%x21] v2 = iconst.i32 2
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; Integer Register-Register Operations.
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; add
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[-,%x7] v10 = iadd v1, v2 ; bin: 015503b3
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[-,%x16] v11 = iadd v2, v1 ; bin: 00aa8833
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; sub
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[-,%x7] v12 = isub v1, v2 ; bin: 415503b3
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[-,%x16] v13 = isub v2, v1 ; bin: 40aa8833
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; and
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[-,%x7] v20 = band v1, v2 ; bin: 015573b3
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[-,%x16] v21 = band v2, v1 ; bin: 00aaf833
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; or
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[-,%x7] v22 = bor v1, v2 ; bin: 015563b3
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[-,%x16] v23 = bor v2, v1 ; bin: 00aae833
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; xor
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[-,%x7] v24 = bxor v1, v2 ; bin: 015543b3
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[-,%x16] v25 = bxor v2, v1 ; bin: 00aac833
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; sll
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[-,%x7] v30 = ishl v1, v2 ; bin: 015513b3
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[-,%x16] v31 = ishl v2, v1 ; bin: 00aa9833
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; srl
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[-,%x7] v32 = ushr v1, v2 ; bin: 015553b3
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[-,%x16] v33 = ushr v2, v1 ; bin: 00aad833
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; sra
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[-,%x7] v34 = sshr v1, v2 ; bin: 415553b3
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[-,%x16] v35 = sshr v2, v1 ; bin: 40aad833
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; slt
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[-,%x7] v42 = icmp slt v1, v2 ; bin: 015523b3
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[-,%x16] v43 = icmp slt v2, v1 ; bin: 00aaa833
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; sltu
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[-,%x7] v44 = icmp ult v1, v2 ; bin: 015533b3
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[-,%x16] v45 = icmp ult v2, v1 ; bin: 00aab833
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; Integer Register-Immediate Instructions
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; addi
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[-,%x7] v100 = iadd_imm v1, 1000 ; bin: 3e850393
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[-,%x16] v101 = iadd_imm v2, -905 ; bin: c77a8813
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; andi
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[-,%x7] v110 = band_imm v1, 1000 ; bin: 3e857393
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[-,%x16] v111 = band_imm v2, -905 ; bin: c77af813
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; ori
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[-,%x7] v112 = bor_imm v1, 1000 ; bin: 3e856393
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[-,%x16] v113 = bor_imm v2, -905 ; bin: c77ae813
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; xori
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[-,%x7] v114 = bxor_imm v1, 1000 ; bin: 3e854393
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[-,%x16] v115 = bxor_imm v2, -905 ; bin: c77ac813
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; slli
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[-,%x7] v120 = ishl_imm v1, 31 ; bin: 01f51393
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[-,%x16] v121 = ishl_imm v2, 8 ; bin: 008a9813
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; srli
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[-,%x7] v122 = ushr_imm v1, 31 ; bin: 01f55393
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[-,%x16] v123 = ushr_imm v2, 8 ; bin: 008ad813
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; srai
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[-,%x7] v124 = sshr_imm v1, 31 ; bin: 41f55393
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[-,%x16] v125 = sshr_imm v2, 8 ; bin: 408ad813
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; slti
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[-,%x7] v130 = icmp_imm slt v1, 1000 ; bin: 3e852393
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[-,%x16] v131 = icmp_imm slt v2, -905 ; bin: c77aa813
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; sltiu
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[-,%x7] v132 = icmp_imm ult v1, 1000 ; bin: 3e853393
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[-,%x16] v133 = icmp_imm ult v2, -905 ; bin: c77ab813
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; lui
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[-,%x7] v140 = iconst.i32 0x12345000 ; bin: 123453b7
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[-,%x16] v141 = iconst.i32 0xffffffff_fedcb000 ; bin: fedcb837
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brz v1, ebb3
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fallthrough ebb1
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; Control Transfer Instructions
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ebb1:
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; beq 0x000
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br_icmp eq v1, v2, ebb1 ; bin: 01550063
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; bne 0xffc
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br_icmp ne v1, v2, ebb1 ; bin: ff551ee3
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; blt 0xff8
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br_icmp slt v1, v2, ebb1 ; bin: ff554ce3
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; bge 0xff4
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br_icmp sge v1, v2, ebb1 ; bin: ff555ae3
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; bltu 0xff0
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br_icmp ult v1, v2, ebb1 ; bin: ff5568e3
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; bgeu 0xfec
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br_icmp uge v1, v2, ebb1 ; bin: ff5576e3
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; Forward branches.
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; beq 0x018
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br_icmp eq v2, v1, ebb2 ; bin: 00aa8c63
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; bne 0x014
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br_icmp ne v2, v1, ebb2 ; bin: 00aa9a63
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; blt 0x010
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br_icmp slt v2, v1, ebb2 ; bin: 00aac863
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; bge 0x00c
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br_icmp sge v2, v1, ebb2 ; bin: 00aad663
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; bltu 0x008
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br_icmp ult v2, v1, ebb2 ; bin: 00aae463
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; bgeu 0x004
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br_icmp uge v2, v1, ebb2 ; bin: 00aaf263
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fallthrough ebb2
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ebb2:
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; jal %x0, 0x00000
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jump ebb2 ; bin: 0000006f
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ebb3:
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; beq x, %x0
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brz v1, ebb3 ; bin: 00050063
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; bne x, %x0
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brnz v1, ebb3 ; bin: fe051ee3
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; jal %x0, 0x1ffff4
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jump ebb2 ; bin: ff5ff06f
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}
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