e8f772c1ac
Previously, in #2128, we factored out a common "vanilla 64-bit ABI" implementation from the AArch64 ABI code, with the idea that this should be largely compatible with x64. This PR alters the new x64 backend to make use of the shared infrastructure, removing the duplication that existed previously. The generated code is nearly (not exactly) the same; the only difference relates to how the clobber-save region is padded in the prologue. This also changes some register allocations in the aarch64 code because call support in the shared ABI infra now passes a temp vreg in, rather than requiring use of a fixed, non-allocable temp; tests have been updated, and the runtime behavior is unchanged.
110 lines
3.3 KiB
Rust
110 lines
3.3 KiB
Rust
//! Compilation backend pipeline: optimized IR to VCode / binemit.
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use crate::ir::Function;
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use crate::machinst::*;
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use crate::settings;
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use crate::timing;
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use log::debug;
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use regalloc::{allocate_registers_with_opts, Algorithm, Options};
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/// Compile the given function down to VCode with allocated registers, ready
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/// for binary emission.
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pub fn compile<B: LowerBackend + MachBackend>(
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f: &Function,
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b: &B,
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abi: Box<dyn ABICallee<I = B::MInst>>,
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) -> CodegenResult<VCode<B::MInst>>
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where
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B::MInst: ShowWithRRU,
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{
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// Compute lowered block order.
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let block_order = BlockLoweringOrder::new(f);
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// Build the lowering context.
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let lower = Lower::new(f, abi, block_order)?;
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// Lower the IR.
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let (mut vcode, stack_map_request_info) = {
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let _tt = timing::vcode_lower();
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lower.lower(b)?
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};
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debug!(
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"vcode from lowering: \n{}",
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vcode.show_rru(Some(b.reg_universe()))
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);
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// Perform register allocation.
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let (run_checker, algorithm) = match vcode.flags().regalloc() {
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settings::Regalloc::Backtracking => (false, Algorithm::Backtracking(Default::default())),
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settings::Regalloc::BacktrackingChecked => {
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(true, Algorithm::Backtracking(Default::default()))
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}
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settings::Regalloc::ExperimentalLinearScan => {
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(false, Algorithm::LinearScan(Default::default()))
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}
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settings::Regalloc::ExperimentalLinearScanChecked => {
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(true, Algorithm::LinearScan(Default::default()))
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}
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};
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#[cfg(feature = "regalloc-snapshot")]
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{
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use std::fs;
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use std::path::Path;
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if let Some(path) = std::env::var("SERIALIZE_REGALLOC").ok() {
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let snapshot = regalloc::IRSnapshot::from_function(&vcode, b.reg_universe());
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let serialized = bincode::serialize(&snapshot).expect("couldn't serialize snapshot");
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let file_path = Path::new(&path).join(Path::new(&format!("ir{}.bin", f.name)));
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fs::write(file_path, &serialized).expect("couldn't write IR snapshot file");
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}
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}
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// If either there are no reference-typed values, or else there are
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// but there are no safepoints at which we need to know about them,
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// then we don't need stack maps.
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let sri = if stack_map_request_info.reftyped_vregs.len() > 0
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&& stack_map_request_info.safepoint_insns.len() > 0
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{
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Some(&stack_map_request_info)
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} else {
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None
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};
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let result = {
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let _tt = timing::regalloc();
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allocate_registers_with_opts(
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&mut vcode,
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b.reg_universe(),
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sri,
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Options {
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run_checker,
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algorithm,
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},
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)
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.map_err(|err| {
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debug!(
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"Register allocation error for vcode\n{}\nError: {:?}",
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vcode.show_rru(Some(b.reg_universe())),
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err
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);
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err
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})
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.expect("register allocation")
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};
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// Reorder vcode into final order and copy out final instruction sequence
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// all at once. This also inserts prologues/epilogues.
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{
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let _tt = timing::vcode_post_ra();
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vcode.replace_insns_from_regalloc(result);
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}
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debug!(
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"vcode after regalloc: final version:\n{}",
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vcode.show_rru(Some(b.reg_universe()))
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);
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Ok(vcode)
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}
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