6286ca7310
When a load/store instruction needs an address of the form `v0 + uextend(v1)` or `v0 + sextend(v1)` (or the commuted forms thereof), we currently generate a separate zero/sign-extend operation and then use a plain `[rA, rB]` addressing mode. This patch extends `lower_address()` to look at both addends of an address if it has two addends and a zero offset, recognize extension operations, and incorporate them directly into a `[rA, rB, UXTW]` or `[rA, rB, SXTW]` form. This should improve our performence on WebAssembly workloads, at least, because we often see a 64-bit linear memory base indexed by a 32-bit (Wasm) pointer value.
59 lines
1.1 KiB
Plaintext
59 lines
1.1 KiB
Plaintext
test compile
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target aarch64
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function %f0(i64, i32) -> i32 {
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block0(v0: i64, v1: i32):
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v2 = uextend.i64 v1
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v3 = load_complex.i32 v0+v2
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return v3
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: ldr w0, [x0, w1, UXTW]
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f1(i64, i32) -> i32 {
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block0(v0: i64, v1: i32):
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v2 = uextend.i64 v1
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v3 = load_complex.i32 v2+v0
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return v3
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: ldr w0, [x0, w1, UXTW]
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f1(i64, i32) -> i32 {
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block0(v0: i64, v1: i32):
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v2 = sextend.i64 v1
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v3 = load_complex.i32 v0+v2
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return v3
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: ldr w0, [x0, w1, SXTW]
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f1(i64, i32) -> i32 {
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block0(v0: i64, v1: i32):
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v2 = sextend.i64 v1
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v3 = load_complex.i32 v2+v0
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return v3
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: ldr w0, [x0, w1, SXTW]
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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