9e088e4164
This patch: * removes the "default" opt level, on the basis that it has no definition and is referred to nowhere in the compiler. * renames the "fastest" level to "none". The resulting set of transformations is unchanged. * renames the "best" level to "speed_and_size". The resulting set of transformations is unchanged. * adds a new level, "speed". This is the same as "speed_and_size" except that it omits transformations aimed only at reducing code size. Currently it omits only the insn shrinking pass.
41 lines
1.1 KiB
Plaintext
41 lines
1.1 KiB
Plaintext
test binemit
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set opt_level=speed_and_size
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target x86_64
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; Test that instruction shrinking eliminates REX prefixes when possible.
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; The binary encodings can be verified with the command:
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;
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; sed -ne 's/^ *; asm: *//p' filetests/isa/x86/shrink.clif | llvm-mc -show-encoding -triple=x86_64
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;
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function %test_shrinking(i32) -> i32 {
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ebb0(v0: i32 [ %rdi ]):
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; asm: movl $0x2,%eax
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[-,%rcx] v1 = iconst.i32 2 ; bin: b9 00000002
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; asm: subl %ecx,%edi
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[-,%rdi] v2 = isub v0, v1 ; bin: 29 cf
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return v2
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}
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function %test_not_shrinking(i32) -> i32 {
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ebb0(v0: i32 [ %r8 ]):
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; asm: movl $0x2,%eax
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[-,%rcx] v1 = iconst.i32 2 ; bin: b9 00000002
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; asm: subl %ecx,%edi
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[-,%r8] v2 = isub v0, v1 ; bin: 41 29 c8
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return v2
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}
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function %test_not_shrinking_i8() {
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ebb0:
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[-,%rsi] v1 = iconst.i8 1
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; asm: movsbl %sil,%esi
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[-,%rsi] v2 = sextend.i32 v1 ; bin: 40 0f be f6
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; asm: movzbl %sil,%esi
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[-,%rsi] v3 = uextend.i32 v1 ; bin: 40 0f b6 f6
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; asm: movzbl %sil,%esi
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[-,%rsi] v4 = uextend.i64 v1 ; bin: 40 0f b6 f6
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trap user0
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}
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