a0318f36f0
This PR switches Cranelift over to the new register allocator, regalloc2. See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801) for a summary of the design changes. This switchover has implications for core VCode/MachInst types and the lowering pass. Overall, this change brings improvements to both compile time and speed of generated code (runtime), as reported in #3942: ``` Benchmark Compilation (wallclock) Execution (wallclock) blake3-scalar 25% faster 28% faster blake3-simd no diff no diff meshoptimizer 19% faster 17% faster pulldown-cmark 17% faster no diff bz2 15% faster no diff SpiderMonkey, 21% faster 2% faster fib(30) clang.wasm 42% faster N/A ```
35 lines
509 B
Plaintext
35 lines
509 B
Plaintext
test compile precise-output
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target x86_64
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function %f(i64) -> i32 {
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block0(v0: i64):
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v1 = ifcmp_sp v0
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brif ugt v1, block1
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jump block2
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block1:
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v2 = iconst.i32 0
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return v2
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block2:
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v3 = iconst.i32 1
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return v3
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}
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; cmpq %rsp, %rdi
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; jnbe label1; j label2
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; block1:
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; xorl %eax, %eax, %eax
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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; block2:
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; movl $1, %eax
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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