435a15b88d
Change the result type for the bit-counting instructions from a fixed i8 to the iB type variable which is the type of the input. This matches the convention in WebAssembly, and at least Intel's instructions will set a full register's worth of count result, even if it is always < 64. Duplicate the Intel 'ur' encoding recipe into 'umr' and 'urm' variants corresponding to the RM and MR encoding variants. The difference is which register is encoded as 'reg' and which is 'r/m' in the ModR/M byte. A 'mov' register copy uses the MR variant, a unary popcnt uses the RM variant.
95 lines
1.5 KiB
Plaintext
95 lines
1.5 KiB
Plaintext
; Test basic code generation for i32 arithmetic WebAssembly instructions.
|
|
test compile
|
|
|
|
set is_64bit=0
|
|
isa intel
|
|
|
|
set is_64bit=1
|
|
isa intel
|
|
|
|
; Constants.
|
|
|
|
function %i32_const() -> i32 {
|
|
ebb0:
|
|
v0 = iconst.i32 0x8765_4321
|
|
return v0
|
|
}
|
|
|
|
; Unary operations.
|
|
|
|
; function %i32_clz(i32) -> i32
|
|
; function %i32_ctz(i32) -> i32
|
|
|
|
function %i32_popcnt(i32) -> i32 {
|
|
ebb0(v0: i32):
|
|
v1 = popcnt v0
|
|
return v1
|
|
}
|
|
|
|
; Binary operations.
|
|
|
|
function %i32_add(i32, i32) -> i32 {
|
|
ebb0(v0: i32, v1: i32):
|
|
v2 = iadd v0, v1
|
|
return v2
|
|
}
|
|
|
|
function %i32_sub(i32, i32) -> i32 {
|
|
ebb0(v0: i32, v1: i32):
|
|
v2 = isub v0, v1
|
|
return v2
|
|
}
|
|
|
|
; function %i32_mul(i32, i32) -> i32
|
|
; function %i32_div(i32, i32) -> i32
|
|
; function %i32_rem_s(i32, i32) -> i32
|
|
; function %i32_rem_u(i32, i32) -> i32
|
|
|
|
function %i32_and(i32, i32) -> i32 {
|
|
ebb0(v0: i32, v1: i32):
|
|
v2 = band v0, v1
|
|
return v2
|
|
}
|
|
|
|
function %i32_or(i32, i32) -> i32 {
|
|
ebb0(v0: i32, v1: i32):
|
|
v2 = bor v0, v1
|
|
return v2
|
|
}
|
|
|
|
function %i32_xor(i32, i32) -> i32 {
|
|
ebb0(v0: i32, v1: i32):
|
|
v2 = bxor v0, v1
|
|
return v2
|
|
}
|
|
|
|
function %i32_shl(i32, i32) -> i32 {
|
|
ebb0(v0: i32, v1: i32):
|
|
v2 = ishl v0, v1
|
|
return v2
|
|
}
|
|
|
|
function %i32_shr_s(i32, i32) -> i32 {
|
|
ebb0(v0: i32, v1: i32):
|
|
v2 = sshr v0, v1
|
|
return v2
|
|
}
|
|
|
|
function %i32_shr_u(i32, i32) -> i32 {
|
|
ebb0(v0: i32, v1: i32):
|
|
v2 = ushr v0, v1
|
|
return v2
|
|
}
|
|
|
|
function %i32_rotl(i32, i32) -> i32 {
|
|
ebb0(v0: i32, v1: i32):
|
|
v2 = rotl v0, v1
|
|
return v2
|
|
}
|
|
|
|
function %i32_rotr(i32, i32) -> i32 {
|
|
ebb0(v0: i32, v1: i32):
|
|
v2 = rotr v0, v1
|
|
return v2
|
|
}
|