* riscv64: Add `Zvl` extensions * riscv64: Allow lowering SIMD operations that fit in a vector register * riscv64: Support non 128bit vector sizes * riscv64: Add Zvl Presets * riscv64: Precompute `min_vec_reg_size`
This crate contains the core Cranelift code generator. It translates code from an intermediate representation into executable machine code.