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wasmtime/cranelift/codegen
Afonso Bordado 4337ccd4b7 riscv64: Support non 128bit vector sizes (#6266)
* riscv64: Add `Zvl` extensions

* riscv64: Allow lowering SIMD operations that fit in a vector register

* riscv64: Support non 128bit vector sizes

* riscv64: Add Zvl Presets

* riscv64: Precompute `min_vec_reg_size`
2023-04-25 14:50:00 +00:00
..
2023-04-05 17:06:36 +00:00
2023-04-21 00:47:58 +00:00

This crate contains the core Cranelift code generator. It translates code from an intermediate representation into executable machine code.