72e2b7fe80
This commit migrates these existing instructions to ISLE from the manual
lowerings implemented today. This was mostly straightforward but while I
was at it I fixed what appeared to be broken translations for I{8,16}
for `clz`, `cls`, and `ctz`. Previously the lowerings would produce
results as-if the input was 32-bits, but now I believe they all
correctly account for the bit-width.
41 lines
703 B
Plaintext
41 lines
703 B
Plaintext
test interpret
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test run
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target aarch64
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target x86_64
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function %clz_i8(i8) -> i8 {
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block0(v0: i8):
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v1 = clz v0
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return v1
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}
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; run: %clz_i8(1) == 7
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; run: %clz_i8(0x40) == 1
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; run: %clz_i8(-1) == 0
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function %clz_i16(i16) -> i16 {
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block0(v0: i16):
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v1 = clz v0
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return v1
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}
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; run: %clz_i16(1) == 15
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; run: %clz_i16(0x4000) == 1
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; run: %clz_i16(-1) == 0
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function %clz_i32(i32) -> i32 {
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block0(v0: i32):
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v1 = clz v0
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return v1
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}
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; run: %clz_i32(1) == 31
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; run: %clz_i32(0x40000000) == 1
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; run: %clz_i32(-1) == 0
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function %clz_i64(i64) -> i64 {
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block0(v0: i64):
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v1 = clz v0
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return v1
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}
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; run: %clz_i64(1) == 63
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; run: %clz_i64(0x4000000000000000) == 1
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; run: %clz_i64(-1) == 0
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