33dba07e6b
This commit migrates the `imul` clif instruction lowering for AArch64 to ISLE. This is a relatively complicated instruction with lots of special cases due to the simd proposal for wasm. Like x64, however, the special casing lends itself to ISLE quite well and the lowerings here in theory are pretty straightforward. The main gotcha of this commit is that this encounters a unique situation which hasn't been encountered yet with other lowerings, namely the `Umlal32` instruction used in the implementation of `i64x2.mul` is unique in the `VecRRRLongOp` class of instructions in that it both reads and writes the destination register (`use_mod` instead of simply `use_def`). This meant that I needed to add another helper in ISLe for creating a `vec_rrrr_long` instruction (despite this enum variant not actually existing) which implicitly moves the first operand into the destination before issuing the actual `VecRRRLong` instruction.
372 lines
16 KiB
Common Lisp
372 lines
16 KiB
Common Lisp
;; aarch64 instruction selection and CLIF-to-MachInst lowering.
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;; The main lowering constructor term: takes a clif `Inst` and returns the
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;; register(s) within which the lowered instruction's result values live.
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(decl lower (Inst) ValueRegs)
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;;;; Rules for `iconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty (iconst (u64_from_imm64 n))))
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(value_reg (imm ty n)))
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;;;; Rules for `bconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty (bconst $false)))
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(value_reg (imm ty 0)))
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(rule (lower (has_type ty (bconst $true)))
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(value_reg (imm ty 1)))
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;;;; Rules for `null` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty (null)))
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(value_reg (imm ty 0)))
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;;;; Rules for `iadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; `i64` and smaller
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;; Base case, simply adding things in registers.
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(rule (lower (has_type (fits_in_64 ty) (iadd x y)))
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(value_reg (alu_rrr (iadd_op ty) (put_in_reg x) (put_in_reg y))))
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;; Special cases for when one operand is an immediate that fits in 12 bits.
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(rule (lower (has_type (fits_in_64 ty) (iadd x (imm12_from_value y))))
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(value_reg (alu_rr_imm12 (iadd_op ty) (put_in_reg x) y)))
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(rule (lower (has_type (fits_in_64 ty) (iadd (imm12_from_value x) y)))
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(value_reg (alu_rr_imm12 (iadd_op ty) (put_in_reg y) x)))
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;; Same as the previous special cases, except we can switch the addition to a
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;; subtraction if the negated immediate fits in 12 bits.
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(rule (lower (has_type (fits_in_64 ty) (iadd x (imm12_from_negated_value y))))
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(value_reg (alu_rr_imm12 (isub_op ty) (put_in_reg x) y)))
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(rule (lower (has_type (fits_in_64 ty) (iadd (imm12_from_negated_value x) y)))
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(value_reg (alu_rr_imm12 (isub_op ty) (put_in_reg y) x)))
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;; Special cases for when we're adding an extended register where the extending
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;; operation can get folded into the add itself.
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(rule (lower (has_type (fits_in_64 ty) (iadd x (extended_value_from_value y))))
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(value_reg (alu_rr_extend_reg (iadd_op ty) (put_in_reg x) y)))
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(rule (lower (has_type (fits_in_64 ty) (iadd (extended_value_from_value x) y)))
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(value_reg (alu_rr_extend_reg (iadd_op ty) (put_in_reg y) x)))
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;; Special cases for when we're adding the shift of a different
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;; register by a constant amount and the shift can get folded into the add.
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(rule (lower (has_type (fits_in_64 ty)
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(iadd x (def_inst (ishl y (def_inst (iconst (lshl_from_imm64 <ty amt))))))))
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(value_reg (alu_rrr_shift (iadd_op ty) (put_in_reg x) (put_in_reg y) amt)))
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(rule (lower (has_type (fits_in_64 ty)
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(iadd (def_inst (ishl x (def_inst (iconst (lshl_from_imm64 <ty amt))))) y)))
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(value_reg (alu_rrr_shift (iadd_op ty) (put_in_reg y) (put_in_reg x) amt)))
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;; Fold an `iadd` and `imul` combination into a `madd` instruction.
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(rule (lower (has_type (fits_in_64 ty) (iadd x (def_inst (imul y z)))))
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(value_reg (alu_rrrr (madd_op ty) (put_in_reg y) (put_in_reg z) (put_in_reg x))))
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(rule (lower (has_type (fits_in_64 ty) (iadd (def_inst (imul x y)) z)))
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(value_reg (alu_rrrr (madd_op ty) (put_in_reg x) (put_in_reg y) (put_in_reg z))))
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;; Helper to use either a 32 or 64-bit add depending on the input type.
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(decl iadd_op (Type) ALUOp)
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(rule (iadd_op (fits_in_32 _ty)) (ALUOp.Add32))
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(rule (iadd_op $I64) (ALUOp.Add64))
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;; Helper to use either a 32 or 64-bit sub depending on the input type.
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(decl isub_op (Type) ALUOp)
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(rule (isub_op (fits_in_32 _ty)) (ALUOp.Sub32))
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(rule (isub_op $I64) (ALUOp.Sub64))
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;; Helper to use either a 32 or 64-bit madd depending on the input type.
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(decl madd_op (Type) ALUOp3)
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(rule (madd_op (fits_in_32 _ty)) (ALUOp3.MAdd32))
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(rule (madd_op $I64) (ALUOp3.MAdd64))
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;; vectors
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(rule (lower (has_type ty @ (multi_lane _ _) (iadd x y)))
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(value_reg (vec_rrr (VecALUOp.Add) (put_in_reg x) (put_in_reg y) (vector_size ty))))
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;; `i128`
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(rule (lower (has_type $I128 (iadd x y)))
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(let (
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;; Get the high/low registers for `x`.
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(x_regs ValueRegs (put_in_regs x))
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(x_lo Reg (value_regs_get x_regs 0))
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(x_hi Reg (value_regs_get x_regs 1))
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;; Get the high/low registers for `y`.
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(y_regs ValueRegs (put_in_regs y))
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(y_lo Reg (value_regs_get y_regs 0))
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(y_hi Reg (value_regs_get y_regs 1))
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)
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;; the actual addition is `adds` followed by `adc` which comprises the
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;; low/high bits of the result
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(with_flags
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(add64_with_flags x_lo y_lo)
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(adc64 x_hi y_hi))))
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;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; `i64` and smaller
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;; Base case, simply subtracting things in registers.
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(rule (lower (has_type (fits_in_64 ty) (isub x y)))
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(value_reg (alu_rrr (isub_op ty) (put_in_reg x) (put_in_reg y))))
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;; Special case for when one operand is an immediate that fits in 12 bits.
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(rule (lower (has_type (fits_in_64 ty) (isub x (imm12_from_value y))))
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(value_reg (alu_rr_imm12 (isub_op ty) (put_in_reg x) y)))
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;; Same as the previous special case, except we can switch the subtraction to an
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;; addition if the negated immediate fits in 12 bits.
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(rule (lower (has_type (fits_in_64 ty) (isub x (imm12_from_negated_value y))))
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(value_reg (alu_rr_imm12 (iadd_op ty) (put_in_reg x) y)))
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;; Special cases for when we're subtracting an extended register where the
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;; extending operation can get folded into the sub itself.
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(rule (lower (has_type (fits_in_64 ty) (isub x (extended_value_from_value y))))
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(value_reg (alu_rr_extend_reg (isub_op ty) (put_in_reg x) y)))
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;; Finally a special case for when we're subtracting the shift of a different
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;; register by a constant amount and the shift can get folded into the sub.
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(rule (lower (has_type (fits_in_64 ty)
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(isub x (def_inst (ishl y (def_inst (iconst (lshl_from_imm64 <ty amt))))))))
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(value_reg (alu_rrr_shift (isub_op ty) (put_in_reg x) (put_in_reg y) amt)))
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;; vectors
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(rule (lower (has_type ty @ (multi_lane _ _) (isub x y)))
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(value_reg (vec_rrr (VecALUOp.Sub) (put_in_reg x) (put_in_reg y) (vector_size ty))))
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;; `i128`
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(rule (lower (has_type $I128 (isub x y)))
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(let (
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;; Get the high/low registers for `x`.
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(x_regs ValueRegs (put_in_regs x))
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(x_lo Reg (value_regs_get x_regs 0))
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(x_hi Reg (value_regs_get x_regs 1))
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;; Get the high/low registers for `y`.
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(y_regs ValueRegs (put_in_regs y))
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(y_lo Reg (value_regs_get y_regs 0))
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(y_hi Reg (value_regs_get y_regs 1))
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)
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;; the actual subtraction is `subs` followed by `sbc` which comprises
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;; the low/high bits of the result
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(with_flags
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(sub64_with_flags x_lo y_lo)
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(sbc64 x_hi y_hi))))
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;;;; Rules for `uadd_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (vec128 ty) (uadd_sat x y)))
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(value_reg (vec_rrr (VecALUOp.Uqadd) (put_in_reg x) (put_in_reg y) (vector_size ty))))
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;;;; Rules for `sadd_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (vec128 ty) (sadd_sat x y)))
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(value_reg (vec_rrr (VecALUOp.Sqadd) (put_in_reg x) (put_in_reg y) (vector_size ty))))
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;;;; Rules for `usub_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (vec128 ty) (usub_sat x y)))
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(value_reg (vec_rrr (VecALUOp.Uqsub) (put_in_reg x) (put_in_reg y) (vector_size ty))))
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;;;; Rules for `ssub_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (vec128 ty) (ssub_sat x y)))
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(value_reg (vec_rrr (VecALUOp.Sqsub) (put_in_reg x) (put_in_reg y) (vector_size ty))))
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;;;; Rules for `ineg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; `i64` and smaller.
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(rule (lower (has_type (fits_in_64 ty) (ineg x)))
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(value_reg (alu_rrr (isub_op ty) (zero_reg) (put_in_reg x))))
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;; vectors.
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(rule (lower (has_type (vec128 ty) (ineg x)))
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(value_reg (vec_misc (VecMisc2.Neg) (put_in_reg x) (vector_size ty))))
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;;;; Rules for `imul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; `i64` and smaller.
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(rule (lower (has_type (fits_in_64 ty) (imul x y)))
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(value_reg (alu_rrrr (madd_op ty) (put_in_reg x) (put_in_reg y) (zero_reg))))
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;; `i128`.
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(rule (lower (has_type $I128 (imul x y)))
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(let (
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;; Get the high/low registers for `x`.
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(x_regs ValueRegs (put_in_regs x))
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(x_lo Reg (value_regs_get x_regs 0))
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(x_hi Reg (value_regs_get x_regs 1))
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;; Get the high/low registers for `y`.
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(y_regs ValueRegs (put_in_regs y))
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(y_lo Reg (value_regs_get y_regs 0))
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(y_hi Reg (value_regs_get y_regs 1))
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;; 128bit mul formula:
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;; dst_lo = x_lo * y_lo
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;; dst_hi = umulhi(x_lo, y_lo) + (x_lo * y_hi) + (x_hi * y_lo)
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;;
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;; We can convert the above formula into the following
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;; umulh dst_hi, x_lo, y_lo
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;; madd dst_hi, x_lo, y_hi, dst_hi
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;; madd dst_hi, x_hi, y_lo, dst_hi
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;; madd dst_lo, x_lo, y_lo, zero
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(dst_hi1 Reg (alu_rrr (ALUOp.UMulH) x_lo y_lo))
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(dst_hi2 Reg (alu_rrrr (ALUOp3.MAdd64) x_lo y_hi dst_hi1))
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(dst_hi Reg (alu_rrrr (ALUOp3.MAdd64) x_hi y_lo dst_hi2))
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(dst_lo Reg (alu_rrrr (ALUOp3.MAdd64) x_lo y_lo (zero_reg)))
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)
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(value_regs dst_lo dst_hi)))
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;; Case for i8x16, i16x8, and i32x4.
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(rule (lower (has_type (vec128 ty @ (not_i64x2)) (imul x y)))
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(value_reg (vec_rrr (VecALUOp.Mul) (put_in_reg x) (put_in_reg y) (vector_size ty))))
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;; Special lowering for i64x2.
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;;
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;; This I64X2 multiplication is performed with several 32-bit
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;; operations.
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;;
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;; 64-bit numbers x and y, can be represented as:
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;; x = a + 2^32(b)
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;; y = c + 2^32(d)
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;;
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;; A 64-bit multiplication is:
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;; x * y = ac + 2^32(ad + bc) + 2^64(bd)
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;; note: `2^64(bd)` can be ignored, the value is too large to fit in
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;; 64 bits.
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;;
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;; This sequence implements a I64X2 multiply, where the registers
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;; `rn` and `rm` are split up into 32-bit components:
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;; rn = |d|c|b|a|
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;; rm = |h|g|f|e|
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;;
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;; rn * rm = |cg + 2^32(ch + dg)|ae + 2^32(af + be)|
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;;
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;; The sequence is:
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;; rev64 rd.4s, rm.4s
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;; mul rd.4s, rd.4s, rn.4s
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;; xtn tmp1.2s, rn.2d
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;; addp rd.4s, rd.4s, rd.4s
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;; xtn tmp2.2s, rm.2d
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;; shll rd.2d, rd.2s, #32
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;; umlal rd.2d, tmp2.2s, tmp1.2s
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(rule (lower (has_type $I64X2 (imul x y)))
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(let (
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(rn Reg (put_in_reg x))
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(rm Reg (put_in_reg y))
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;; Reverse the 32-bit elements in the 64-bit words.
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;; rd = |g|h|e|f|
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(rev Reg (vec_misc (VecMisc2.Rev64) rm (VectorSize.Size32x4)))
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;; Calculate the high half components.
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;; rd = |dg|ch|be|af|
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;;
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;; Note that this 32-bit multiply of the high half
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;; discards the bits that would overflow, same as
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;; if 64-bit operations were used. Also the Shll
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;; below would shift out the overflow bits anyway.
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(mul Reg (vec_rrr (VecALUOp.Mul) rev rn (VectorSize.Size32x4)))
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;; Extract the low half components of rn.
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;; tmp1 = |c|a|
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(tmp1 Reg (vec_rr_narrow (VecRRNarrowOp.Xtn64) rn $false))
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;; Sum the respective high half components.
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;; rd = |dg+ch|be+af||dg+ch|be+af|
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(sum Reg (vec_rrr (VecALUOp.Addp) mul mul (VectorSize.Size32x4)))
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;; Extract the low half components of rm.
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;; tmp2 = |g|e|
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(tmp2 Reg (vec_rr_narrow (VecRRNarrowOp.Xtn64) rm $false))
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;; Shift the high half components, into the high half.
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;; rd = |dg+ch << 32|be+af << 32|
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(shift Reg (vec_rr_long (VecRRLongOp.Shll32) sum $false))
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;; Multiply the low components together, and accumulate with the high
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;; half.
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;; rd = |rd[1] + cg|rd[0] + ae|
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(result Reg (vec_rrrr_long (VecRRRLongOp.Umlal32) shift tmp2 tmp1 $false))
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)
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(value_reg result)))
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;; Special case for `i16x8.extmul_low_i8x16_s`.
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(rule (lower (has_type $I16X8
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(imul (def_inst (swiden_low x @ (value_type $I8X16)))
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(def_inst (swiden_low y @ (value_type $I8X16))))))
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(value_reg (vec_rrr_long (VecRRRLongOp.Smull8) (put_in_reg x) (put_in_reg y) $false)))
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;; Special case for `i16x8.extmul_high_i8x16_s`.
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(rule (lower (has_type $I16X8
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(imul (def_inst (swiden_high x @ (value_type $I8X16)))
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(def_inst (swiden_high y @ (value_type $I8X16))))))
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(value_reg (vec_rrr_long (VecRRRLongOp.Smull8) (put_in_reg x) (put_in_reg y) $true)))
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;; Special case for `i16x8.extmul_low_i8x16_u`.
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(rule (lower (has_type $I16X8
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(imul (def_inst (uwiden_low x @ (value_type $I8X16)))
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(def_inst (uwiden_low y @ (value_type $I8X16))))))
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(value_reg (vec_rrr_long (VecRRRLongOp.Umull8) (put_in_reg x) (put_in_reg y) $false)))
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;; Special case for `i16x8.extmul_high_i8x16_u`.
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(rule (lower (has_type $I16X8
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(imul (def_inst (uwiden_high x @ (value_type $I8X16)))
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(def_inst (uwiden_high y @ (value_type $I8X16))))))
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(value_reg (vec_rrr_long (VecRRRLongOp.Umull8) (put_in_reg x) (put_in_reg y) $true)))
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;; Special case for `i32x4.extmul_low_i16x8_s`.
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(rule (lower (has_type $I32X4
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(imul (def_inst (swiden_low x @ (value_type $I16X8)))
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(def_inst (swiden_low y @ (value_type $I16X8))))))
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(value_reg (vec_rrr_long (VecRRRLongOp.Smull16) (put_in_reg x) (put_in_reg y) $false)))
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;; Special case for `i32x4.extmul_high_i16x8_s`.
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(rule (lower (has_type $I32X4
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(imul (def_inst (swiden_high x @ (value_type $I16X8)))
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(def_inst (swiden_high y @ (value_type $I16X8))))))
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(value_reg (vec_rrr_long (VecRRRLongOp.Smull16) (put_in_reg x) (put_in_reg y) $true)))
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;; Special case for `i32x4.extmul_low_i16x8_u`.
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(rule (lower (has_type $I32X4
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(imul (def_inst (uwiden_low x @ (value_type $I16X8)))
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(def_inst (uwiden_low y @ (value_type $I16X8))))))
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(value_reg (vec_rrr_long (VecRRRLongOp.Umull16) (put_in_reg x) (put_in_reg y) $false)))
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;; Special case for `i32x4.extmul_high_i16x8_u`.
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(rule (lower (has_type $I32X4
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(imul (def_inst (uwiden_high x @ (value_type $I16X8)))
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(def_inst (uwiden_high y @ (value_type $I16X8))))))
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(value_reg (vec_rrr_long (VecRRRLongOp.Umull16) (put_in_reg x) (put_in_reg y) $true)))
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;; Special case for `i64x2.extmul_low_i32x4_s`.
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(rule (lower (has_type $I64X2
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(imul (def_inst (swiden_low x @ (value_type $I32X4)))
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(def_inst (swiden_low y @ (value_type $I32X4))))))
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(value_reg (vec_rrr_long (VecRRRLongOp.Smull32) (put_in_reg x) (put_in_reg y) $false)))
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;; Special case for `i64x2.extmul_high_i32x4_s`.
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(rule (lower (has_type $I64X2
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(imul (def_inst (swiden_high x @ (value_type $I32X4)))
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(def_inst (swiden_high y @ (value_type $I32X4))))))
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(value_reg (vec_rrr_long (VecRRRLongOp.Smull32) (put_in_reg x) (put_in_reg y) $true)))
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;; Special case for `i64x2.extmul_low_i32x4_u`.
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|
(rule (lower (has_type $I64X2
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|
(imul (def_inst (uwiden_low x @ (value_type $I32X4)))
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(def_inst (uwiden_low y @ (value_type $I32X4))))))
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(value_reg (vec_rrr_long (VecRRRLongOp.Umull32) (put_in_reg x) (put_in_reg y) $false)))
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|
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;; Special case for `i64x2.extmul_high_i32x4_u`.
|
|
(rule (lower (has_type $I64X2
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|
(imul (def_inst (uwiden_high x @ (value_type $I32X4)))
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(def_inst (uwiden_high y @ (value_type $I32X4))))))
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(value_reg (vec_rrr_long (VecRRRLongOp.Umull32) (put_in_reg x) (put_in_reg y) $true)))
|