cdecc858b4
Add a RISC-V 64 (`riscv64`, RV64GC) backend. Co-authored-by: yuyang <756445638@qq.com> Co-authored-by: Chris Fallin <chris@cfallin.org> Co-authored-by: Afonso Bordado <afonsobordado@az8.co>
145 lines
3.6 KiB
Plaintext
145 lines
3.6 KiB
Plaintext
test interpret
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test run
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; Test these inputs without div traps, it shouldn't affect normal inputs
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set avoid_div_traps
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target aarch64
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target s390x
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target x86_64
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target riscv64
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function %srem_i64(i64, i64) -> i64 {
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block0(v0: i64,v1: i64):
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v2 = srem v0, v1
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return v2
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}
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; run: %srem_i64(0, 1) == 0
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; run: %srem_i64(2, 2) == 0
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; run: %srem_i64(1, -1) == 0
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; run: %srem_i64(3, 2) == 1
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; run: %srem_i64(19, 7) == 5
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; run: %srem_i64(3, -2) == 1
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; run: %srem_i64(-19, 7) == -5
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; run: %srem_i64(-57, -5) == -2
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; run: %srem_i64(0, 104857600000) == 0
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; run: %srem_i64(104857600000, 511) == 398
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; run: %srem_i64(0xC0FFEEEE_DECAFFFF, 8) == -1
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; run: %srem_i64(0xC0FFEEEE_DECAFFFF, -8) == -1
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; run: %srem_i64(0x80000000_00000000, -2) == 0
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function %srem_i32(i32, i32) -> i32 {
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block0(v0: i32,v1: i32):
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v2 = srem v0, v1
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return v2
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}
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; run: %srem_i32(0, 1) == 0
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; run: %srem_i32(2, 2) == 0
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; run: %srem_i32(1, -1) == 0
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; run: %srem_i32(3, 2) == 1
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; run: %srem_i32(19, 7) == 5
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; run: %srem_i32(3, -2) == 1
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; run: %srem_i32(-19, 7) == -5
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; run: %srem_i32(0, 13) == 0
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; run: %srem_i32(1048576, 8192) == 0
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; run: %srem_i32(-1024, 255) == -4
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; run: %srem_i32(0xC0FFEEEE, 8) == -2
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; run: %srem_i32(0xC0FFEEEE, -8) == -2
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; run: %srem_i32(0x80000000, -2) == 0
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function %srem_i16(i16, i16) -> i16 {
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block0(v0: i16,v1: i16):
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v2 = srem v0, v1
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return v2
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}
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; run: %srem_i16(0, 1) == 0
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; run: %srem_i16(2, 2) == 0
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; run: %srem_i16(1, -1) == 0
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; run: %srem_i16(3, 2) == 1
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; run: %srem_i16(19, 7) == 5
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; run: %srem_i16(3, -2) == 1
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; run: %srem_i16(13, 5) == 3
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; run: %srem_i16(0, 42) == 0
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; run: %srem_i16(4, -2) == 0
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; run: %srem_i16(-19, 7) == -5
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; run: %srem_i16(0xC0FF, 8) == -1
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; run: %srem_i16(0xC0FF, -8) == -1
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; run: %srem_i16(0x8000, -2) == 0
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function %srem_i8(i8, i8) -> i8 {
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block0(v0: i8,v1: i8):
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v2 = srem v0, v1
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return v2
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}
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; run: %srem_i8(0, 1) == 0
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; run: %srem_i8(2, 2) == 0
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; run: %srem_i8(1, -1) == 0
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; run: %srem_i8(2, 7) == 2
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; run: %srem_i8(3, 2) == 1
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; run: %srem_i8(19, 7) == 5
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; run: %srem_i8(3, -2) == 1
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; run: %srem_i8(-19, 7) == -5
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; run: %srem_i8(0xC0, 8) == 0
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; run: %srem_i8(0xC0, -8) == 0
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; run: %srem_i8(0x80, -2) == 0
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function %srem_imm_i64(i64) -> i64 {
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block0(v0: i64):
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v1 = srem_imm v0, 3
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return v1
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}
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; run: %srem_imm_i64(0) == 0
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; run: %srem_imm_i64(1) == 1
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; run: %srem_imm_i64(2) == 2
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; run: %srem_imm_i64(3) == 0
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; run: %srem_imm_i64(19) == 1
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; run: %srem_imm_i64(-19) == -1
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; run: %srem_imm_i64(-57) == 0
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; run: %srem_imm_i64(104857600000) == 1
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; run: %srem_imm_i64(0xC0FFEEEE_DECAFFFF) == -1
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; run: %srem_imm_i64(0x80000000_00000000) == -2
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function %srem_imm_i32(i32) -> i32 {
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block0(v0: i32):
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v1 = srem_imm v0, 3
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return v1
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}
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; run: %srem_imm_i32(0) == 0
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; run: %srem_imm_i32(1) == 1
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; run: %srem_imm_i32(2) == 2
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; run: %srem_imm_i32(3) == 0
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; run: %srem_imm_i32(4) == 1
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; run: %srem_imm_i32(19) == 1
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; run: %srem_imm_i32(-19) == -1
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; run: %srem_imm_i32(-42) == 0
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; run: %srem_imm_i32(1057) == 1
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; run: %srem_imm_i32(0xC0FFEEEE) == -2
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function %srem_imm_i16(i16) -> i16 {
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block0(v0: i16):
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v1 = srem_imm v0, 3
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return v1
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}
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; run: %srem_imm_i16(0) == 0
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; run: %srem_imm_i16(1) == 1
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; run: %srem_imm_i16(2) == 2
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; run: %srem_imm_i16(3) == 0
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; run: %srem_imm_i16(4) == 1
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; run: %srem_imm_i16(19) == 1
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; run: %srem_imm_i16(-19) == -1
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; run: %srem_imm_i16(0xC0FF) == -1
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; run: %srem_imm_i16(0x8000) == -2
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function %srem_imm_i8(i8) -> i8 {
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block0(v0: i8):
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v1 = srem_imm v0, 3
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return v1
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}
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; run: %srem_imm_i8(0) == 0
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; run: %srem_imm_i8(1) == 1
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; run: %srem_imm_i8(2) == 2
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; run: %srem_imm_i8(3) == 0
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; run: %srem_imm_i8(19) == 1
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; run: %srem_imm_i8(-19) == -1
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; run: %srem_imm_i8(0xC0) == -1
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; run: %srem_imm_i8(0x80) == -2
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