0508932174
* cranelift: Reorganize test suite Group some SIMD operations by instruction. * cranelift: Deduplicate some shift tests Also, new tests with the mod behaviour * aarch64: Lower shifts with mod behaviour * x64: Lower shifts with mod behaviour * wasmtime: Don't mask SIMD shifts
47 lines
1.2 KiB
Plaintext
47 lines
1.2 KiB
Plaintext
test run
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set enable_simd
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target aarch64
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target s390x
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target x86_64 skylake
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function %ishl_i8x16(i8x16, i32) -> i8x16 {
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block0(v0: i8x16, v1: i32):
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v2 = ishl v0, v1
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return v2
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}
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; run: %ishl_i8x16([0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15], 4) == [0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xa0 0xb0 0xc0 0xd0 0xe0 0xf0]
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; run: %ishl_i8x16([0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15], 12) == [0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xa0 0xb0 0xc0 0xd0 0xe0 0xf0]
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function %ishl_i16x8(i16x8, i32) -> i16x8 {
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block0(v0: i16x8, v1: i32):
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v2 = ishl v0, v1
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return v2
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}
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; run: %ishl_i16x8([1 2 4 8 16 32 64 128], 1) == [2 4 8 16 32 64 128 256]
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; run: %ishl_i16x8([1 2 4 8 16 32 64 128], 17) == [2 4 8 16 32 64 128 256]
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function %ishl_i32x4(i32x4, i32) -> i32x4 {
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block0(v0: i32x4, v1: i32):
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v2 = ishl v0, v1
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return v2
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}
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; run: %ishl_i32x4([1 2 4 8], 1) == [2 4 8 16]
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; run: %ishl_i32x4([1 2 4 8], 33) == [2 4 8 16]
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function %ishl_i64x2(i64x2, i32) -> i64x2 {
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block0(v0: i64x2, v1: i32):
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v2 = ishl v0, v1
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return v2
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}
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; run: %ishl_i64x2([1 2], 1) == [2 4]
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; run: %ishl_i64x2([1 2], 65) == [2 4]
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function %ishl_imm_i64x2(i64x2) -> i64x2 {
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block0(v0: i64x2):
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v2 = ishl_imm v0, 1
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return v2
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}
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; run: %ishl_imm_i64x2([1 0]) == [2 0]
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