073c727a74
This end result was previously enacted by carrying a `SourceLoc` on every load/store, which was somewhat cumbersome, and only indirectly encoded metadata about a memory reference (can it trap) by its presence or absence. We have a type for this -- `MemFlags` -- that tells us everything we might want to know about a load or store, and we should plumb it through to code emission instead. This PR attaches a `MemFlags` to an `Amode` on x64, and puts it on load and store `Inst` variants on aarch64. These two choices seem to factor things out in the nicest way: there are relatively few load/store insts on aarch64 but many addressing modes, while the opposite is true on x64.
126 lines
4.3 KiB
Rust
126 lines
4.3 KiB
Rust
use crate::isa::unwind::input::UnwindInfo;
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use crate::isa::x64::inst::{
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args::{AluRmiROpcode, Amode, RegMemImm, SyntheticAmode},
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regs, Inst,
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};
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use crate::machinst::{UnwindInfoContext, UnwindInfoGenerator};
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use crate::result::CodegenResult;
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use alloc::vec::Vec;
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use regalloc::Reg;
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#[cfg(feature = "unwind")]
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pub(crate) mod systemv;
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pub struct X64UnwindInfo;
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impl UnwindInfoGenerator<Inst> for X64UnwindInfo {
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fn create_unwind_info(
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context: UnwindInfoContext<Inst>,
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) -> CodegenResult<Option<UnwindInfo<Reg>>> {
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use crate::isa::unwind::input::{self, UnwindCode};
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let mut codes = Vec::new();
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const WORD_SIZE: u8 = 8;
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for i in context.prologue.clone() {
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let i = i as usize;
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let inst = &context.insts[i];
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let offset = context.insts_layout[i];
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match inst {
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Inst::Push64 {
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src: RegMemImm::Reg { reg },
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} => {
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codes.push((
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offset,
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UnwindCode::StackAlloc {
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size: WORD_SIZE.into(),
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},
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));
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codes.push((
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offset,
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UnwindCode::SaveRegister {
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reg: *reg,
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stack_offset: 0,
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},
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));
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}
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Inst::MovRR { src, dst, .. } => {
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if *src == regs::rsp() {
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codes.push((offset, UnwindCode::SetFramePointer { reg: dst.to_reg() }));
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}
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}
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Inst::AluRmiR {
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is_64: true,
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op: AluRmiROpcode::Sub,
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src: RegMemImm::Imm { simm32 },
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dst,
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..
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} if dst.to_reg() == regs::rsp() => {
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let imm = *simm32;
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codes.push((offset, UnwindCode::StackAlloc { size: imm }));
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}
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Inst::MovRM {
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src,
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dst: SyntheticAmode::Real(Amode::ImmReg { simm32, base, .. }),
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..
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} if *base == regs::rsp() => {
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// `mov reg, imm(rsp)`
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let imm = *simm32;
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codes.push((
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offset,
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UnwindCode::SaveRegister {
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reg: *src,
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stack_offset: imm,
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},
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));
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}
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Inst::AluRmiR {
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is_64: true,
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op: AluRmiROpcode::Add,
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src: RegMemImm::Imm { simm32 },
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dst,
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..
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} if dst.to_reg() == regs::rsp() => {
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let imm = *simm32;
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codes.push((offset, UnwindCode::StackDealloc { size: imm }));
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}
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_ => {}
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}
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}
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let last_epilogue_end = context.len;
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let epilogues_unwind_codes = context
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.epilogues
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.iter()
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.map(|epilogue| {
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// TODO add logic to process epilogue instruction instead of
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// returning empty array.
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let end = epilogue.end as usize - 1;
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let end_offset = context.insts_layout[end];
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if end_offset == last_epilogue_end {
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// Do not remember/restore for very last epilogue.
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return vec![];
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}
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let start = epilogue.start as usize;
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let offset = context.insts_layout[start];
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vec![
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(offset, UnwindCode::RememberState),
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// TODO epilogue instructions
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(end_offset, UnwindCode::RestoreState),
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]
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})
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.collect();
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let prologue_size = context.insts_layout[context.prologue.end as usize];
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Ok(Some(input::UnwindInfo {
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prologue_size,
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prologue_unwind_codes: codes,
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epilogues_unwind_codes,
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function_size: context.len,
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word_size: WORD_SIZE,
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initial_sp_offset: WORD_SIZE,
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}))
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}
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}
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