3ef30b5b67
This brings these instructions with our general naming convention of signed instructions being prefixed with `s`.
322 lines
9.8 KiB
Rust
322 lines
9.8 KiB
Rust
//! Lower a single Cranelift instruction into vcode.
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use crate::ir::Inst as IRInst;
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use crate::ir::Opcode;
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use crate::isa::aarch64::inst::*;
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use crate::isa::aarch64::settings as aarch64_settings;
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use crate::machinst::lower::*;
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use crate::machinst::*;
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use crate::settings::Flags;
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use crate::{CodegenError, CodegenResult};
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use target_lexicon::Triple;
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/// Actually codegen an instruction's results into registers.
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pub(crate) fn lower_insn_to_regs(
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ctx: &mut Lower<Inst>,
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insn: IRInst,
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triple: &Triple,
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flags: &Flags,
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isa_flags: &aarch64_settings::Flags,
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) -> CodegenResult<()> {
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let op = ctx.data(insn).opcode();
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let outputs = insn_outputs(ctx, insn);
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let ty = if outputs.len() > 0 {
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Some(ctx.output_ty(insn, 0))
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} else {
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None
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};
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if let Ok(()) = super::lower::isle::lower(ctx, triple, flags, isa_flags, &outputs, insn) {
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return Ok(());
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}
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let implemented_in_isle = |ctx: &mut Lower<Inst>| -> ! {
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unreachable!(
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"implemented in ISLE: inst = `{}`, type = `{:?}`",
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ctx.dfg().display_inst(insn),
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ty
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);
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};
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match op {
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Opcode::Iconst | Opcode::Null => implemented_in_isle(ctx),
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Opcode::F32const => {
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let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
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let val = ctx.get_constant(insn).unwrap();
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for inst in
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Inst::load_fp_constant32(rd, val as u32, |ty| ctx.alloc_tmp(ty).only_reg().unwrap())
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{
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ctx.emit(inst);
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}
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}
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Opcode::F64const => {
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let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
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let val = ctx.get_constant(insn).unwrap();
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for inst in
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Inst::load_fp_constant64(rd, val, |ty| ctx.alloc_tmp(ty).only_reg().unwrap())
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{
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ctx.emit(inst);
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}
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}
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Opcode::GetFramePointer | Opcode::GetStackPointer | Opcode::GetReturnAddress => {
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implemented_in_isle(ctx)
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}
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Opcode::Iadd => implemented_in_isle(ctx),
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Opcode::Isub => implemented_in_isle(ctx),
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Opcode::UaddSat | Opcode::SaddSat | Opcode::UsubSat | Opcode::SsubSat => {
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implemented_in_isle(ctx)
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}
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Opcode::Ineg => implemented_in_isle(ctx),
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Opcode::Imul => implemented_in_isle(ctx),
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Opcode::Umulhi | Opcode::Smulhi => implemented_in_isle(ctx),
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Opcode::Udiv | Opcode::Sdiv | Opcode::Urem | Opcode::Srem => implemented_in_isle(ctx),
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Opcode::Uextend | Opcode::Sextend => implemented_in_isle(ctx),
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Opcode::Bnot => implemented_in_isle(ctx),
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Opcode::Band
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| Opcode::Bor
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| Opcode::Bxor
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| Opcode::BandNot
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| Opcode::BorNot
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| Opcode::BxorNot => implemented_in_isle(ctx),
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Opcode::Ishl | Opcode::Ushr | Opcode::Sshr => implemented_in_isle(ctx),
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Opcode::Rotr | Opcode::Rotl => implemented_in_isle(ctx),
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Opcode::Bitrev | Opcode::Clz | Opcode::Cls | Opcode::Ctz => implemented_in_isle(ctx),
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Opcode::Bswap => implemented_in_isle(ctx),
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Opcode::Popcnt => implemented_in_isle(ctx),
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Opcode::Load
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| Opcode::Uload8
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| Opcode::Sload8
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| Opcode::Uload16
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| Opcode::Sload16
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| Opcode::Uload32
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| Opcode::Sload32
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| Opcode::Sload8x8
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| Opcode::Uload8x8
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| Opcode::Sload16x4
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| Opcode::Uload16x4
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| Opcode::Sload32x2
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| Opcode::Uload32x2 => implemented_in_isle(ctx),
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Opcode::Store | Opcode::Istore8 | Opcode::Istore16 | Opcode::Istore32 => {
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implemented_in_isle(ctx)
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}
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Opcode::StackAddr => implemented_in_isle(ctx),
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Opcode::DynamicStackAddr => implemented_in_isle(ctx),
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Opcode::AtomicRmw => implemented_in_isle(ctx),
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Opcode::AtomicCas => implemented_in_isle(ctx),
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Opcode::AtomicLoad => implemented_in_isle(ctx),
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Opcode::AtomicStore => implemented_in_isle(ctx),
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Opcode::Fence => implemented_in_isle(ctx),
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Opcode::StackLoad
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| Opcode::StackStore
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| Opcode::DynamicStackStore
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| Opcode::DynamicStackLoad => {
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panic!("Direct stack memory access not supported; should not be used by Wasm");
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}
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Opcode::HeapAddr => {
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panic!("heap_addr should have been removed by legalization!");
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}
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Opcode::TableAddr => {
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panic!("table_addr should have been removed by legalization!");
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}
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Opcode::Nop => {
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// Nothing.
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}
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Opcode::Select => implemented_in_isle(ctx),
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Opcode::SelectSpectreGuard => implemented_in_isle(ctx),
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Opcode::Bitselect | Opcode::Vselect => implemented_in_isle(ctx),
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Opcode::IsNull | Opcode::IsInvalid => implemented_in_isle(ctx),
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Opcode::Ireduce => implemented_in_isle(ctx),
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Opcode::Bmask => implemented_in_isle(ctx),
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Opcode::Bitcast => implemented_in_isle(ctx),
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Opcode::Return => implemented_in_isle(ctx),
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Opcode::Ifcmp | Opcode::Ffcmp => {
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// An Ifcmp/Ffcmp must always be seen as a use of a brif/brff or trueif/trueff
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// instruction. This will always be the case as long as the IR uses an Ifcmp/Ffcmp from
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// the same block, or a dominating block. In other words, it cannot pass through a BB
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// param (phi). The flags pass of the verifier will ensure this.
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panic!("Should never reach ifcmp as isel root!");
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}
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Opcode::Icmp => implemented_in_isle(ctx),
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Opcode::Fcmp => implemented_in_isle(ctx),
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Opcode::Debugtrap => implemented_in_isle(ctx),
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Opcode::Trap | Opcode::ResumableTrap => implemented_in_isle(ctx),
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Opcode::Trapz | Opcode::Trapnz | Opcode::ResumableTrapnz => {
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panic!("trapz / trapnz / resumable_trapnz should have been removed by legalization!");
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}
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Opcode::FuncAddr => implemented_in_isle(ctx),
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Opcode::GlobalValue => {
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panic!("global_value should have been removed by legalization!");
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}
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Opcode::SymbolValue => implemented_in_isle(ctx),
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Opcode::Call | Opcode::CallIndirect => implemented_in_isle(ctx),
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Opcode::GetPinnedReg | Opcode::SetPinnedReg => implemented_in_isle(ctx),
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Opcode::Jump | Opcode::Brz | Opcode::Brnz | Opcode::BrTable => {
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panic!("Branch opcode reached non-branch lowering logic!");
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}
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Opcode::Vconst => implemented_in_isle(ctx),
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Opcode::Extractlane => implemented_in_isle(ctx),
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Opcode::Insertlane => implemented_in_isle(ctx),
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Opcode::Splat => implemented_in_isle(ctx),
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Opcode::ScalarToVector => implemented_in_isle(ctx),
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Opcode::VallTrue | Opcode::VanyTrue => implemented_in_isle(ctx),
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Opcode::VhighBits => implemented_in_isle(ctx),
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Opcode::Shuffle => implemented_in_isle(ctx),
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Opcode::Swizzle => implemented_in_isle(ctx),
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Opcode::Isplit => implemented_in_isle(ctx),
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Opcode::Iconcat => implemented_in_isle(ctx),
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Opcode::Smax | Opcode::Umax | Opcode::Umin | Opcode::Smin => implemented_in_isle(ctx),
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Opcode::IaddPairwise => implemented_in_isle(ctx),
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Opcode::WideningPairwiseDotProductS => implemented_in_isle(ctx),
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Opcode::Fadd | Opcode::Fsub | Opcode::Fmul | Opcode::Fdiv | Opcode::Fmin | Opcode::Fmax => {
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implemented_in_isle(ctx)
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}
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Opcode::FminPseudo | Opcode::FmaxPseudo => implemented_in_isle(ctx),
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Opcode::Sqrt | Opcode::Fneg | Opcode::Fabs | Opcode::Fpromote | Opcode::Fdemote => {
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implemented_in_isle(ctx)
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}
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Opcode::Ceil | Opcode::Floor | Opcode::Trunc | Opcode::Nearest => implemented_in_isle(ctx),
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Opcode::Fma => implemented_in_isle(ctx),
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Opcode::Fcopysign => implemented_in_isle(ctx),
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Opcode::FcvtToUint | Opcode::FcvtToSint => implemented_in_isle(ctx),
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Opcode::FcvtFromUint | Opcode::FcvtFromSint => implemented_in_isle(ctx),
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Opcode::FcvtToUintSat | Opcode::FcvtToSintSat => implemented_in_isle(ctx),
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Opcode::IaddIfcout => implemented_in_isle(ctx),
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Opcode::UaddOverflowTrap => implemented_in_isle(ctx),
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Opcode::IaddImm
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| Opcode::ImulImm
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| Opcode::UdivImm
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| Opcode::SdivImm
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| Opcode::UremImm
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| Opcode::SremImm
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| Opcode::IrsubImm
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| Opcode::IaddCin
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| Opcode::IaddIfcin
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| Opcode::IaddCout
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| Opcode::IaddCarry
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| Opcode::IaddIfcarry
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| Opcode::IsubBin
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| Opcode::IsubIfbin
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| Opcode::IsubBout
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| Opcode::IsubIfbout
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| Opcode::IsubBorrow
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| Opcode::IsubIfborrow
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| Opcode::BandImm
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| Opcode::BorImm
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| Opcode::BxorImm
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| Opcode::RotlImm
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| Opcode::RotrImm
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| Opcode::IshlImm
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| Opcode::UshrImm
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| Opcode::SshrImm
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| Opcode::IcmpImm
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| Opcode::IfcmpImm => {
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panic!("ALU+imm and ALU+carry ops should not appear here!");
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}
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Opcode::Iabs => implemented_in_isle(ctx),
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Opcode::AvgRound => implemented_in_isle(ctx),
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Opcode::Snarrow | Opcode::Unarrow | Opcode::Uunarrow => implemented_in_isle(ctx),
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Opcode::SwidenLow | Opcode::SwidenHigh | Opcode::UwidenLow | Opcode::UwidenHigh => {
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implemented_in_isle(ctx)
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}
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Opcode::TlsValue => implemented_in_isle(ctx),
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Opcode::SqmulRoundSat => implemented_in_isle(ctx),
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Opcode::FcvtLowFromSint => implemented_in_isle(ctx),
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Opcode::FvpromoteLow => implemented_in_isle(ctx),
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Opcode::Fvdemote => implemented_in_isle(ctx),
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Opcode::ExtractVector => implemented_in_isle(ctx),
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Opcode::Vconcat | Opcode::Vsplit => {
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return Err(CodegenError::Unsupported(format!(
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"Unimplemented lowering: {}",
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op
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)));
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}
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}
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Ok(())
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}
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