ed3157f508
The offset is relative to the stack pointer in the calling function, so it excludes the return address pushed by the call instruction itself on Intel ISAs. Change the ArgumentLoc::Stack offset to an i32, so it matches the stack slot offsets.
177 lines
4.4 KiB
Plaintext
177 lines
4.4 KiB
Plaintext
test cat
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; The smallest possible function.
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function %minimal() {
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ebb0:
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trap
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}
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; sameln: function %minimal() {
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; nextln: ebb0:
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; nextln: trap
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; nextln: }
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; Create and use values.
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; Polymorphic instructions with type suffix.
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function %ivalues() {
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ebb0:
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v0 = iconst.i32 2
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v1 = iconst.i8 6
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v2 = ishl v0, v1
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}
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; sameln: function %ivalues() {
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; nextln: ebb0:
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; nextln: $v0 = iconst.i32 2
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; nextln: $v1 = iconst.i8 6
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; nextln: $v2 = ishl $v0, $v1
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; nextln: }
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; Polymorphic istruction controlled by second operand.
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function %select() {
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ebb0(v90: i32, v91: i32, v92: b1):
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v0 = select v92, v90, v91
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}
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; sameln: function %select() {
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; nextln: ebb0($v90: i32, $v91: i32, $v92: b1):
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; nextln: $v0 = select $v92, $v90, $v91
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; nextln: }
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; Lane indexes.
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function %lanes() {
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ebb0:
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v0 = iconst.i32x4 2
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v1 = extractlane v0, 3
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v2 = insertlane v0, 1, v1
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}
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; sameln: function %lanes() {
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; nextln: ebb0:
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; nextln: $v0 = iconst.i32x4 2
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; nextln: $v1 = extractlane $v0, 3
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; nextln: $v2 = insertlane $v0, 1, $v1
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; nextln: }
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; Integer condition codes.
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function %icmp(i32, i32) {
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ebb0(v90: i32, v91: i32):
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v0 = icmp eq v90, v91
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v1 = icmp ult v90, v91
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v2 = icmp_imm sge v90, -12
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v3 = irsub_imm v91, 45
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br_icmp eq v90, v91, ebb0(v91, v90)
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}
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; sameln: function %icmp(i32, i32) {
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; nextln: ebb0($v90: i32, $v91: i32):
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; nextln: $v0 = icmp eq $v90, $v91
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; nextln: $v1 = icmp ult $v90, $v91
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; nextln: $v2 = icmp_imm sge $v90, -12
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; nextln: $v3 = irsub_imm $v91, 45
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; nextln: br_icmp eq $v90, $v91, ebb0($v91, $v90)
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; nextln: }
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; Floating condition codes.
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function %fcmp(f32, f32) {
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ebb0(v90: f32, v91: f32):
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v0 = fcmp eq v90, v91
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v1 = fcmp uno v90, v91
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v2 = fcmp lt v90, v91
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}
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; sameln: function %fcmp(f32, f32) {
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; nextln: ebb0($v90: f32, $v91: f32):
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; nextln: $v0 = fcmp eq $v90, $v91
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; nextln: $v1 = fcmp uno $v90, $v91
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; nextln: $v2 = fcmp lt $v90, $v91
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; nextln: }
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; The bitcast instruction has two type variables: The controlling type variable
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; controls the outout type, and the input type is a free variable.
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function %bitcast(i32, f32) {
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ebb0(v90: i32, v91: f32):
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v0 = bitcast.i8x4 v90
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v1 = bitcast.i32 v91
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}
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; sameln: function %bitcast(i32, f32) {
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; nextln: ebb0($v90: i32, $v91: f32):
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; nextln: $v0 = bitcast.i8x4 $v90
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; nextln: $v1 = bitcast.i32 $v91
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; nextln: }
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; Stack slot references
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function %stack() {
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ss10 = spill_slot 8
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ss2 = local 4
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ss3 = incoming_arg 4, offset 8
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ss4 = outgoing_arg 4
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ebb0:
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v1 = stack_load.i32 ss10
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v2 = stack_load.i32 ss10+4
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stack_store v1, ss10+2
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stack_store v2, ss2
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}
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; sameln: function %stack() {
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; nextln: $ss10 = spill_slot 8
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; nextln: $ss2 = local 4
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; nextln: $ss3 = incoming_arg 4, offset 8
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; nextln: $ss4 = outgoing_arg 4
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; check: ebb0:
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; nextln: $v1 = stack_load.i32 $ss10
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; nextln: $v2 = stack_load.i32 $ss10+4
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; nextln: stack_store $v1, $ss10+2
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; nextln: stack_store $v2, $ss2
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; Heap access instructions.
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function %heap(i32) {
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; TODO: heap0 = heap %foo
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ebb0(v1: i32):
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v2 = heap_load.f32 v1
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v3 = heap_load.f32 v1+12
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heap_store v3, v1
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}
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; sameln: function %heap(i32) {
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; nextln: ebb0($v1: i32):
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; nextln: $v2 = heap_load.f32 $v1
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; nextln: $v3 = heap_load.f32 $v1+12
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; nextln: heap_store $v3, $v1
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; Memory access instructions.
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function %memory(i32) {
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ebb0(v1: i32):
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v2 = load.i64 v1
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v3 = load.i64 aligned v1
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v4 = load.i64 notrap v1
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v5 = load.i64 notrap aligned v1
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v6 = load.i64 aligned notrap v1
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v7 = load.i64 v1-12
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v8 = load.i64 notrap v1+0x1_0000
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store v2, v1
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store aligned v3, v1+12
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store notrap aligned v3, v1-12
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}
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; sameln: function %memory(i32) {
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; nextln: ebb0($v1: i32):
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; nextln: $v2 = load.i64 $v1
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; nextln: $v3 = load.i64 aligned $v1
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; nextln: $v4 = load.i64 notrap $v1
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; nextln: $v5 = load.i64 notrap aligned $v1
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; nextln: $v6 = load.i64 notrap aligned $v1
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; nextln: $v7 = load.i64 $v1-12
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; nextln: $v8 = load.i64 notrap $v1+0x0001_0000
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; nextln: store $v2, $v1
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; nextln: store aligned $v3, $v1+12
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; nextln: store notrap aligned $v3, $v1-12
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; Register diversions.
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; This test file has no ISA, so we can unly use register unit numbers.
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function %diversion(i32) {
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ebb0(v1: i32):
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regmove v1, %10 -> %20
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regmove v1, %20 -> %10
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return
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}
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; sameln: function %diversion(i32) {
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; nextln: ebb0($v1: i32):
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; nextln: regmove $v1, %10 -> %20
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; nextln: regmove $v1, %20 -> %10
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; nextln: return
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; nextln: }
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