* cranelift-native: Move riscv to separate module * cranelift-native: Read /proc/cpuinfo to parse RISC-V extensions * ci: Add QEMU cpuinfo emulation patch This patch emulates the /proc/cpuinfo interface for RISC-V. This allows us to do feature detection for the RISC-V backend. It has been queued for QEMU 8.1 so we should remove it as soon as that is available. * ci: Enable QEMU RISC-V extensions * cranelift-native: Cleanup ISA string parsing Co-Authored-By: Jamey Sharp <jsharp@fastly.com> * cranelift-native: Rework `/proc/cpuinfo` parsing Co-Authored-By: Jamey Sharp <jsharp@fastly.com> --------- Co-authored-by: Jamey Sharp <jsharp@fastly.com>
218 lines
8.0 KiB
Rust
218 lines
8.0 KiB
Rust
//! Performs autodetection of the host for the purposes of running
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//! Cranelift to generate code to run on the same machine.
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#![deny(
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missing_docs,
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trivial_numeric_casts,
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unused_extern_crates,
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unstable_features
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)]
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#![warn(unused_import_braces)]
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#![cfg_attr(feature = "clippy", plugin(clippy(conf_file = "../../clippy.toml")))]
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#![cfg_attr(feature = "cargo-clippy", allow(clippy::new_without_default))]
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#![cfg_attr(
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feature = "cargo-clippy",
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warn(
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clippy::float_arithmetic,
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clippy::mut_mut,
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clippy::nonminimal_bool,
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clippy::map_unwrap_or,
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clippy::clippy::print_stdout,
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clippy::unicode_not_nfc,
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clippy::use_self
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)
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)]
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use cranelift_codegen::isa;
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use cranelift_codegen::settings::Configurable;
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use target_lexicon::Triple;
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#[cfg(all(target_arch = "riscv64", target_os = "linux"))]
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mod riscv;
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/// Return an `isa` builder configured for the current host
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/// machine, or `Err(())` if the host machine is not supported
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/// in the current configuration.
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pub fn builder() -> Result<isa::Builder, &'static str> {
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builder_with_options(true)
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}
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/// Return an `isa` builder configured for the current host
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/// machine, or `Err(())` if the host machine is not supported
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/// in the current configuration.
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///
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/// Selects the given backend variant specifically; this is
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/// useful when more than oen backend exists for a given target
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/// (e.g., on x86-64).
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pub fn builder_with_options(infer_native_flags: bool) -> Result<isa::Builder, &'static str> {
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let mut isa_builder = isa::lookup(Triple::host()).map_err(|err| match err {
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isa::LookupError::SupportDisabled => "support for architecture disabled at compile time",
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isa::LookupError::Unsupported => "unsupported architecture",
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})?;
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if infer_native_flags {
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self::infer_native_flags(&mut isa_builder)?;
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}
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Ok(isa_builder)
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}
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/// Return an `isa` builder configured for the current host
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/// machine, or `Err(())` if the host machine is not supported
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/// in the current configuration.
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///
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/// Selects the given backend variant specifically; this is
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/// useful when more than oen backend exists for a given target
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/// (e.g., on x86-64).
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pub fn infer_native_flags(isa_builder: &mut dyn Configurable) -> Result<(), &'static str> {
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#[cfg(target_arch = "x86_64")]
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{
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if !std::is_x86_feature_detected!("sse2") {
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return Err("x86 support requires SSE2");
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}
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// These are temporarily enabled by default (see #3810 for
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// more) so that a default-constructed `Flags` can work with
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// default Wasmtime features. Otherwise, the user must
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// explicitly use native flags or turn these on when on x86-64
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// platforms to avoid a configuration panic. In order for the
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// "enable if detected" logic below to work, we must turn them
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// *off* (differing from the default) and then re-enable below
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// if present.
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isa_builder.set("has_sse3", "false").unwrap();
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isa_builder.set("has_ssse3", "false").unwrap();
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isa_builder.set("has_sse41", "false").unwrap();
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isa_builder.set("has_sse42", "false").unwrap();
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if std::is_x86_feature_detected!("sse3") {
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isa_builder.enable("has_sse3").unwrap();
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}
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if std::is_x86_feature_detected!("ssse3") {
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isa_builder.enable("has_ssse3").unwrap();
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}
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if std::is_x86_feature_detected!("sse4.1") {
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isa_builder.enable("has_sse41").unwrap();
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}
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if std::is_x86_feature_detected!("sse4.2") {
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isa_builder.enable("has_sse42").unwrap();
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}
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if std::is_x86_feature_detected!("popcnt") {
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isa_builder.enable("has_popcnt").unwrap();
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}
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if std::is_x86_feature_detected!("avx") {
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isa_builder.enable("has_avx").unwrap();
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}
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if std::is_x86_feature_detected!("avx2") {
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isa_builder.enable("has_avx2").unwrap();
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}
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if std::is_x86_feature_detected!("fma") {
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isa_builder.enable("has_fma").unwrap();
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}
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if std::is_x86_feature_detected!("bmi1") {
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isa_builder.enable("has_bmi1").unwrap();
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}
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if std::is_x86_feature_detected!("bmi2") {
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isa_builder.enable("has_bmi2").unwrap();
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}
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if std::is_x86_feature_detected!("avx512bitalg") {
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isa_builder.enable("has_avx512bitalg").unwrap();
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}
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if std::is_x86_feature_detected!("avx512dq") {
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isa_builder.enable("has_avx512dq").unwrap();
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}
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if std::is_x86_feature_detected!("avx512f") {
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isa_builder.enable("has_avx512f").unwrap();
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}
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if std::is_x86_feature_detected!("avx512vl") {
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isa_builder.enable("has_avx512vl").unwrap();
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}
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if std::is_x86_feature_detected!("avx512vbmi") {
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isa_builder.enable("has_avx512vbmi").unwrap();
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}
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if std::is_x86_feature_detected!("lzcnt") {
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isa_builder.enable("has_lzcnt").unwrap();
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}
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}
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#[cfg(target_arch = "aarch64")]
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{
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if std::arch::is_aarch64_feature_detected!("lse") {
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isa_builder.enable("has_lse").unwrap();
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}
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if std::arch::is_aarch64_feature_detected!("paca") {
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isa_builder.enable("has_pauth").unwrap();
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}
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if cfg!(target_os = "macos") {
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// Pointer authentication is always available on Apple Silicon.
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isa_builder.enable("sign_return_address").unwrap();
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// macOS enforces the use of the B key for return addresses.
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isa_builder.enable("sign_return_address_with_bkey").unwrap();
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}
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}
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// There is no is_s390x_feature_detected macro yet, so for now
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// we use getauxval from the libc crate directly.
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#[cfg(all(target_arch = "s390x", target_os = "linux"))]
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{
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let v = unsafe { libc::getauxval(libc::AT_HWCAP) };
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const HWCAP_S390X_VXRS_EXT2: libc::c_ulong = 32768;
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if (v & HWCAP_S390X_VXRS_EXT2) != 0 {
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isa_builder.enable("has_vxrs_ext2").unwrap();
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// There is no separate HWCAP bit for mie2, so assume
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// that any machine with vxrs_ext2 also has mie2.
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isa_builder.enable("has_mie2").unwrap();
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}
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}
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// `is_riscv_feature_detected` is nightly only for now, use
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// getauxval from the libc crate directly as a temporary measure.
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#[cfg(all(target_arch = "riscv64", target_os = "linux"))]
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{
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// Try both hwcap and cpuinfo
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// HWCAP only returns single letter extensions, cpuinfo returns all of
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// them but may not be available in some systems (QEMU < 8.1).
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riscv::hwcap_detect(isa_builder)?;
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// Ignore errors for cpuinfo. QEMU versions prior to 8.1 do not emulate
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// the cpuinfo interface, so we can't rely on it being present for now.
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let _ = riscv::cpuinfo_detect(isa_builder);
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}
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Ok(())
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}
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#[cfg(test)]
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mod tests {
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use super::builder;
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use cranelift_codegen::isa::CallConv;
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use cranelift_codegen::settings;
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#[test]
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fn test() {
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if let Ok(isa_builder) = builder() {
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let flag_builder = settings::builder();
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let isa = isa_builder
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.finish(settings::Flags::new(flag_builder))
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.unwrap();
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if cfg!(all(target_os = "macos", target_arch = "aarch64")) {
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assert_eq!(isa.default_call_conv(), CallConv::AppleAarch64);
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} else if cfg!(any(unix, target_os = "nebulet")) {
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assert_eq!(isa.default_call_conv(), CallConv::SystemV);
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} else if cfg!(windows) {
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assert_eq!(isa.default_call_conv(), CallConv::WindowsFastcall);
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}
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if cfg!(target_pointer_width = "64") {
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assert_eq!(isa.pointer_bits(), 64);
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} else if cfg!(target_pointer_width = "32") {
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assert_eq!(isa.pointer_bits(), 32);
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} else if cfg!(target_pointer_width = "16") {
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assert_eq!(isa.pointer_bits(), 16);
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}
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}
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}
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}
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/// Version number of this crate.
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pub const VERSION: &str = env!("CARGO_PKG_VERSION");
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