43a86f14d5
This also paves the way for unifying TargetIsa and MachBackend, since now they map one to one. In theory the two traits could be merged, which would be nice to limit the number of total concepts. Also they have quite different responsibilities, so it might be fine to keep them separate. Interestingly, this PR started as removing RegInfo from the TargetIsa trait since the adapter returned a dummy value there. From the fallout, noticed that all Display implementations didn't needed an ISA anymore (since these were only used to render ISA specific registers). Also the whole family of RegInfo / ValueLoc / RegUnit was exclusively used for the old backend, and these could be removed. Notably, some IR instructions needed to be removed, because they were using RegUnit too: this was the oddball of regfill / regmove / regspill / copy_special, which were IR instructions inserted by the old regalloc. Fare thee well!
292 lines
9.2 KiB
Rust
292 lines
9.2 KiB
Rust
//! ARM 64-bit Instruction Set Architecture.
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use crate::ir::condcodes::IntCC;
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use crate::ir::Function;
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use crate::isa::aarch64::settings as aarch64_settings;
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use crate::isa::Builder as IsaBuilder;
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use crate::machinst::{
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compile, MachBackend, MachCompileResult, MachTextSectionBuilder, TargetIsaAdapter,
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TextSectionBuilder, VCode,
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};
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use crate::result::CodegenResult;
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use crate::settings as shared_settings;
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use alloc::{boxed::Box, vec::Vec};
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use regalloc::{PrettyPrint, RealRegUniverse};
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use target_lexicon::{Aarch64Architecture, Architecture, Triple};
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// New backend:
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mod abi;
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pub(crate) mod inst;
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mod lower;
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mod lower_inst;
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mod settings;
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use inst::create_reg_universe;
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use self::inst::EmitInfo;
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/// An AArch64 backend.
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pub struct AArch64Backend {
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triple: Triple,
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flags: shared_settings::Flags,
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isa_flags: aarch64_settings::Flags,
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reg_universe: RealRegUniverse,
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}
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impl AArch64Backend {
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/// Create a new AArch64 backend with the given (shared) flags.
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pub fn new_with_flags(
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triple: Triple,
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flags: shared_settings::Flags,
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isa_flags: aarch64_settings::Flags,
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) -> AArch64Backend {
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let reg_universe = create_reg_universe(&flags);
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AArch64Backend {
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triple,
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flags,
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isa_flags,
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reg_universe,
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}
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}
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/// This performs lowering to VCode, register-allocates the code, computes block layout and
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/// finalizes branches. The result is ready for binary emission.
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fn compile_vcode(
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&self,
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func: &Function,
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flags: shared_settings::Flags,
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) -> CodegenResult<VCode<inst::Inst>> {
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let emit_info = EmitInfo::new(flags.clone());
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let abi = Box::new(abi::AArch64ABICallee::new(func, flags)?);
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compile::compile::<AArch64Backend>(func, self, abi, emit_info)
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}
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}
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impl MachBackend for AArch64Backend {
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fn compile_function(
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&self,
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func: &Function,
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want_disasm: bool,
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) -> CodegenResult<MachCompileResult> {
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let flags = self.flags();
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let vcode = self.compile_vcode(func, flags.clone())?;
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let (buffer, bb_starts, bb_edges) = vcode.emit();
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let frame_size = vcode.frame_size();
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let stackslot_offsets = vcode.stackslot_offsets().clone();
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let disasm = if want_disasm {
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Some(vcode.show_rru(Some(&create_reg_universe(flags))))
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} else {
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None
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};
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let buffer = buffer.finish();
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Ok(MachCompileResult {
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buffer,
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frame_size,
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disasm,
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value_labels_ranges: Default::default(),
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stackslot_offsets,
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bb_starts,
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bb_edges,
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})
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}
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fn name(&self) -> &'static str {
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"aarch64"
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}
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fn triple(&self) -> Triple {
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self.triple.clone()
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}
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fn flags(&self) -> &shared_settings::Flags {
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&self.flags
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}
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fn isa_flags(&self) -> Vec<shared_settings::Value> {
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self.isa_flags.iter().collect()
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}
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fn reg_universe(&self) -> &RealRegUniverse {
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&self.reg_universe
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}
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fn unsigned_add_overflow_condition(&self) -> IntCC {
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// Unsigned `>=`; this corresponds to the carry flag set on aarch64, which happens on
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// overflow of an add.
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IntCC::UnsignedGreaterThanOrEqual
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}
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#[cfg(feature = "unwind")]
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fn emit_unwind_info(
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&self,
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result: &MachCompileResult,
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kind: crate::machinst::UnwindInfoKind,
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) -> CodegenResult<Option<crate::isa::unwind::UnwindInfo>> {
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use crate::isa::unwind::UnwindInfo;
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use crate::machinst::UnwindInfoKind;
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Ok(match kind {
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UnwindInfoKind::SystemV => {
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let mapper = self::inst::unwind::systemv::RegisterMapper;
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Some(UnwindInfo::SystemV(
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crate::isa::unwind::systemv::create_unwind_info_from_insts(
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&result.buffer.unwind_info[..],
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result.buffer.data.len(),
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&mapper,
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)?,
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))
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}
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UnwindInfoKind::Windows => {
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// TODO: support Windows unwind info on AArch64
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None
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}
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_ => None,
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})
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}
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#[cfg(feature = "unwind")]
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fn create_systemv_cie(&self) -> Option<gimli::write::CommonInformationEntry> {
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Some(inst::unwind::systemv::create_cie())
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}
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fn text_section_builder(&self, num_funcs: u32) -> Box<dyn TextSectionBuilder> {
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Box::new(MachTextSectionBuilder::<inst::Inst>::new(num_funcs))
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}
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}
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/// Create a new `isa::Builder`.
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pub fn isa_builder(triple: Triple) -> IsaBuilder {
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assert!(triple.architecture == Architecture::Aarch64(Aarch64Architecture::Aarch64));
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IsaBuilder {
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triple,
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setup: aarch64_settings::builder(),
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constructor: |triple, shared_flags, builder| {
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let isa_flags = aarch64_settings::Flags::new(&shared_flags, builder);
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let backend = AArch64Backend::new_with_flags(triple, shared_flags, isa_flags);
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Box::new(TargetIsaAdapter::new(backend))
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},
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}
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}
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#[cfg(test)]
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mod test {
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use super::*;
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use crate::cursor::{Cursor, FuncCursor};
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use crate::ir::types::*;
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use crate::ir::{AbiParam, ExternalName, Function, InstBuilder, Signature};
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use crate::isa::CallConv;
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use crate::settings;
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use crate::settings::Configurable;
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use core::str::FromStr;
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use target_lexicon::Triple;
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#[test]
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fn test_compile_function() {
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let name = ExternalName::testcase("test0");
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let mut sig = Signature::new(CallConv::SystemV);
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sig.params.push(AbiParam::new(I32));
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sig.returns.push(AbiParam::new(I32));
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let mut func = Function::with_name_signature(name, sig);
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let bb0 = func.dfg.make_block();
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let arg0 = func.dfg.append_block_param(bb0, I32);
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let mut pos = FuncCursor::new(&mut func);
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pos.insert_block(bb0);
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let v0 = pos.ins().iconst(I32, 0x1234);
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let v1 = pos.ins().iadd(arg0, v0);
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pos.ins().return_(&[v1]);
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let mut shared_flags_builder = settings::builder();
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shared_flags_builder.set("opt_level", "none").unwrap();
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let shared_flags = settings::Flags::new(shared_flags_builder);
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let isa_flags = aarch64_settings::Flags::new(&shared_flags, aarch64_settings::builder());
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let backend = AArch64Backend::new_with_flags(
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Triple::from_str("aarch64").unwrap(),
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shared_flags,
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isa_flags,
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);
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let buffer = backend.compile_function(&mut func, false).unwrap().buffer;
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let code = &buffer.data[..];
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// mov x1, #0x1234
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// add w0, w0, w1
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// ret
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let golden = vec![
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0x81, 0x46, 0x82, 0xd2, 0x00, 0x00, 0x01, 0x0b, 0xc0, 0x03, 0x5f, 0xd6,
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];
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assert_eq!(code, &golden[..]);
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}
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#[test]
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fn test_branch_lowering() {
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let name = ExternalName::testcase("test0");
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let mut sig = Signature::new(CallConv::SystemV);
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sig.params.push(AbiParam::new(I32));
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sig.returns.push(AbiParam::new(I32));
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let mut func = Function::with_name_signature(name, sig);
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let bb0 = func.dfg.make_block();
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let arg0 = func.dfg.append_block_param(bb0, I32);
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let bb1 = func.dfg.make_block();
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let bb2 = func.dfg.make_block();
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let bb3 = func.dfg.make_block();
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let mut pos = FuncCursor::new(&mut func);
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pos.insert_block(bb0);
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let v0 = pos.ins().iconst(I32, 0x1234);
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let v1 = pos.ins().iadd(arg0, v0);
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pos.ins().brnz(v1, bb1, &[]);
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pos.ins().jump(bb2, &[]);
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pos.insert_block(bb1);
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pos.ins().brnz(v1, bb2, &[]);
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pos.ins().jump(bb3, &[]);
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pos.insert_block(bb2);
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let v2 = pos.ins().iadd(v1, v0);
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pos.ins().brnz(v2, bb2, &[]);
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pos.ins().jump(bb1, &[]);
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pos.insert_block(bb3);
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let v3 = pos.ins().isub(v1, v0);
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pos.ins().return_(&[v3]);
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let mut shared_flags_builder = settings::builder();
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shared_flags_builder.set("opt_level", "none").unwrap();
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let shared_flags = settings::Flags::new(shared_flags_builder);
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let isa_flags = aarch64_settings::Flags::new(&shared_flags, aarch64_settings::builder());
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let backend = AArch64Backend::new_with_flags(
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Triple::from_str("aarch64").unwrap(),
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shared_flags,
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isa_flags,
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);
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let result = backend
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.compile_function(&mut func, /* want_disasm = */ false)
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.unwrap();
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let code = &result.buffer.data[..];
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// mov x1, #0x1234 // #4660
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// add w0, w0, w1
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// mov w1, w0
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// cbnz x1, 0x28
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// mov x1, #0x1234 // #4660
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// add w1, w0, w1
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// mov w1, w1
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// cbnz x1, 0x18
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// mov w1, w0
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// cbnz x1, 0x18
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// mov x1, #0x1234 // #4660
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// sub w0, w0, w1
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// ret
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let golden = vec![
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129, 70, 130, 210, 0, 0, 1, 11, 225, 3, 0, 42, 161, 0, 0, 181, 129, 70, 130, 210, 1, 0,
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1, 11, 225, 3, 1, 42, 161, 255, 255, 181, 225, 3, 0, 42, 97, 255, 255, 181, 129, 70,
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130, 210, 0, 0, 1, 75, 192, 3, 95, 214,
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];
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assert_eq!(code, &golden[..]);
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}
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}
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