Add a RISC-V 64 (`riscv64`, RV64GC) backend. Co-authored-by: yuyang <756445638@qq.com> Co-authored-by: Chris Fallin <chris@cfallin.org> Co-authored-by: Afonso Bordado <afonsobordado@az8.co>
17 lines
624 B
Plaintext
17 lines
624 B
Plaintext
test run
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target aarch64
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target riscv64
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target s390x
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function %bxor_not_i128(i128, i128) -> i128 {
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block0(v0: i128, v1: i128):
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v2 = bxor_not v0, v1
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return v2
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}
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; run: %bxor_not_i128(0, 0) == -1
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; run: %bxor_not_i128(-1, 0) == 0
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; run: %bxor_not_i128(-1, -1) == -1
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; run: %bxor_not_i128(-1, 0xFFFFFFFF_FFFFFFFF_00000000_00000000) == 0xFFFFFFFF_FFFFFFFF_00000000_00000000
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; run: %bxor_not_i128(0xFEDCBA98_76543210_01234567_89ABCDEF, 0x01234567_89ABCDEF_FEDCBA98_76543210) == 0
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; run: %bxor_not_i128(0x9440A07D_9440A07D_8FA50A64_8FA50A64, 0xB575A07D_B575A07D_B0A51B75_B0A51B75) == 0xDECAFFFF_DECAFFFF_C0FFEEEE_C0FFEEEE
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