a0318f36f0
This PR switches Cranelift over to the new register allocator, regalloc2. See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801) for a summary of the design changes. This switchover has implications for core VCode/MachInst types and the lowering pass. Overall, this change brings improvements to both compile time and speed of generated code (runtime), as reported in #3942: ``` Benchmark Compilation (wallclock) Execution (wallclock) blake3-scalar 25% faster 28% faster blake3-simd no diff no diff meshoptimizer 19% faster 17% faster pulldown-cmark 17% faster no diff bz2 15% faster no diff SpiderMonkey, 21% faster 2% faster fib(30) clang.wasm 42% faster N/A ```
44 lines
1.2 KiB
Rust
44 lines
1.2 KiB
Rust
//! Miscellaneous helpers for machine backends.
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use super::{InsnOutput, LowerCtx, VCodeInst, ValueRegs};
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use super::{Reg, Writable};
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use crate::ir::Type;
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use std::ops::{Add, BitAnd, Not, Sub};
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/// Returns the size (in bits) of a given type.
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pub fn ty_bits(ty: Type) -> usize {
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usize::from(ty.bits())
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}
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/// Is the type represented by an integer (not float) at the machine level?
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pub(crate) fn ty_has_int_representation(ty: Type) -> bool {
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ty.is_int() || ty.is_bool() || ty.is_ref()
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}
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/// Is the type represented by a float or vector value at the machine level?
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pub(crate) fn ty_has_float_or_vec_representation(ty: Type) -> bool {
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ty.is_vector() || ty.is_float()
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}
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/// Allocate a register for an instruction output and return it.
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pub(crate) fn get_output_reg<I: VCodeInst, C: LowerCtx<I = I>>(
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ctx: &mut C,
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spec: InsnOutput,
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) -> ValueRegs<Writable<Reg>> {
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ctx.get_output(spec.insn, spec.output)
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}
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/// Align a size up to a power-of-two alignment.
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pub(crate) fn align_to<N>(x: N, alignment: N) -> N
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where
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N: Not<Output = N>
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+ BitAnd<N, Output = N>
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+ Add<N, Output = N>
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+ Sub<N, Output = N>
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+ From<u8>
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+ Copy,
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{
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let alignment_mask = alignment - 1.into();
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(x + alignment_mask) & !alignment_mask
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}
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