482 lines
10 KiB
Plaintext
482 lines
10 KiB
Plaintext
test compile
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set unwind_info=false
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set enable_probestack=false
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target aarch64
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function %f1(i64) -> i64 {
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fn0 = %g(i64) -> i64
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block0(v0: i64):
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v1 = call fn0(v0)
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: ldr x1, 8 ; b 12 ; data
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; nextln: blr x1
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f2(i32) -> i64 {
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fn0 = %g(i32 uext) -> i64 baldrdash_system_v
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block0(v0: i32):
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v1 = call fn0(v0)
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; check: mov w0, w0
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; nextln: ldr x1, 8 ; b 12 ; data
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; nextln: blr x1
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; check: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f3(i32) -> i32 uext baldrdash_system_v {
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block0(v0: i32):
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return v0
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}
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; check: mov w0, w0
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function %f4(i32) -> i64 {
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fn0 = %g(i32 sext) -> i64 baldrdash_system_v
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block0(v0: i32):
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v1 = call fn0(v0)
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; check: sxtw x0, w0
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; nextln: ldr x1, 8 ; b 12 ; data
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; nextln: blr x1
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; check: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f5(i32) -> i32 sext baldrdash_system_v {
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block0(v0: i32):
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return v0
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}
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; check: sxtw x0, w0
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function %f6(i8) -> i64 {
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fn0 = %g(i32, i32, i32, i32, i32, i32, i32, i32, i8 sext) -> i64
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block0(v0: i8):
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v1 = iconst.i32 42
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v2 = call fn0(v1, v1, v1, v1, v1, v1, v1, v1, v0)
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov x8, x0
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; nextln: sub sp, sp, #16
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; nextln: virtual_sp_offset_adjust 16
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; nextln: movz x0, #42
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; nextln: movz x1, #42
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; nextln: movz x2, #42
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; nextln: movz x3, #42
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; nextln: movz x4, #42
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; nextln: movz x5, #42
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; nextln: movz x6, #42
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; nextln: movz x7, #42
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; nextln: sturb w8, [sp]
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; nextln: ldr x8, 8 ; b 12 ; data
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; nextln: blr x8
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; nextln: add sp, sp, #16
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; nextln: virtual_sp_offset_adjust -16
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f7(i8) -> i32, i32, i32, i32, i32, i32, i32, i32, i8 sext {
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block0(v0: i8):
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v1 = iconst.i32 42
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return v1, v1, v1, v1, v1, v1, v1, v1, v0
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov x9, x0
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; nextln: mov x8, x1
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; nextln: movz x0, #42
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; nextln: movz x1, #42
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; nextln: movz x2, #42
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; nextln: movz x3, #42
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; nextln: movz x4, #42
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; nextln: movz x5, #42
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; nextln: movz x6, #42
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; nextln: movz x7, #42
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; nextln: sturb w9, [x8]
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f8() {
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fn0 = %g0() -> f32
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fn1 = %g1() -> f64
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fn2 = %g2()
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fn3 = %g3(f32)
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fn4 = %g4(f64)
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block0:
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v0 = call fn0()
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v1 = call fn1()
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v2 = call fn1()
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call fn2()
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call fn3(v0)
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call fn4(v1)
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call fn4(v2)
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return
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sub sp, sp, #32
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; nextln: ldr x0, 8 ; b 12 ; data
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; nextln: blr x0
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; nextln: str s0, [sp]
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; nextln: ldr x0, 8 ; b 12 ; data
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; nextln: blr x0
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; nextln: str d0, [sp, #8]
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; nextln: ldr x0, 8 ; b 12 ; data
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; nextln: blr x0
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; nextln: str d0, [sp, #16]
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; nextln: ldr x0, 8 ; b 12 ; data
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; nextln: blr x0
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; nextln: ldr s0, [sp]
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; nextln: ldr x0, 8 ; b 12 ; data
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; nextln: blr x0
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; nextln: ldr d0, [sp, #8]
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; nextln: ldr x0, 8 ; b 12 ; data
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; nextln: blr x0
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; nextln: ldr d0, [sp, #16]
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; nextln: ldr x0, 8 ; b 12 ; data
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; nextln: blr x0
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; nextln: add sp, sp, #32
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f9() {
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fn0 = %g0() -> i8x16
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fn1 = %g1()
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fn2 = %g2(i8x16)
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block0:
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v0 = call fn0()
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v1 = call fn0()
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v2 = call fn0()
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call fn1()
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call fn2(v0)
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call fn2(v1)
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call fn2(v2)
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return
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sub sp, sp, #48
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; nextln: ldr x0, 8 ; b 12 ; data
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; nextln: blr x0
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; nextln: str q0, [sp]
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; nextln: ldr x0, 8 ; b 12 ; data
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; nextln: blr x0
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; nextln: str q0, [sp, #16]
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; nextln: ldr x0, 8 ; b 12 ; data
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; nextln: blr x0
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; nextln: str q0, [sp, #32]
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; nextln: ldr x0, 8 ; b 12 ; data
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; nextln: blr x0
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; nextln: ldr q0, [sp]
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; nextln: ldr x0, 8 ; b 12 ; data
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; nextln: blr x0
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; nextln: ldr q0, [sp, #16]
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; nextln: ldr x0, 8 ; b 12 ; data
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; nextln: blr x0
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; nextln: ldr q0, [sp, #32]
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; nextln: ldr x0, 8 ; b 12 ; data
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; nextln: blr x0
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; nextln: add sp, sp, #48
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f10() {
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fn0 = %g0() -> f32
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fn1 = %g1() -> f64
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fn2 = %g2() -> i8x16
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fn3 = %g3()
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fn4 = %g4(f32)
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fn5 = %g5(f64)
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fn6 = %g6(i8x16)
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block0:
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v0 = call fn0()
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v1 = call fn1()
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v2 = call fn2()
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call fn3()
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call fn4(v0)
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call fn5(v1)
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call fn6(v2)
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return
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sub sp, sp, #32
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; nextln: ldr x0, 8 ; b 12 ; data
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; nextln: blr x0
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; nextln: str s0, [sp]
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; nextln: ldr x0, 8 ; b 12 ; data
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; nextln: blr x0
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; nextln: str d0, [sp, #8]
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; nextln: ldr x0, 8 ; b 12 ; data
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; nextln: blr x0
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; nextln: str q0, [sp, #16]
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; nextln: ldr x0, 8 ; b 12 ; data
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; nextln: blr x0
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; nextln: ldr s0, [sp]
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; nextln: ldr x0, 8 ; b 12 ; data
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; nextln: blr x0
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; nextln: ldr d0, [sp, #8]
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; nextln: ldr x0, 8 ; b 12 ; data
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; nextln: blr x0
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; nextln: ldr q0, [sp, #16]
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; nextln: ldr x0, 8 ; b 12 ; data
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; nextln: blr x0
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; nextln: add sp, sp, #32
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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; i128 tests
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function %f11(i128, i64) -> i64 {
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block0(v0: i128, v1: i64):
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v2, v3 = isplit v0
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return v3
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov x0, x1
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f11_call(i64) -> i64 {
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fn0 = %f11(i128, i64) -> i64
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block0(v0: i64):
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v1 = iconst.i64 42
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v2 = iconcat v1, v0
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v3 = call fn0(v2, v1)
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return v3
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov x1, x0
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; nextln: movz x0, #42
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; nextln: movz x2, #42
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; nextln: ldr x3, 8 ; b 12 ; data
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; nextln: blr x3
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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; The AArch64 ABI requires that the i128 argument be aligned
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; and to be passed in x2 and x3
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function %f12(i64, i128) -> i64 {
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block0(v0: i64, v1: i128):
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v2, v3 = isplit v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov x0, x2
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f12_call(i64) -> i64 {
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fn0 = %f12(i64, i128) -> i64
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block0(v0: i64):
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v1 = iconst.i64 42
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v2 = iconcat v0, v1
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v3 = call fn0(v1, v2)
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return v3
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: movz x3, #42
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; nextln: mov x2, x0
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; nextln: movz x0, #42
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; nextln: ldr x1, 8 ; b 12 ; data
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; nextln: blr x1
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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; The Apple AArch64 ABI allows the i128 argument to not be aligned
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; and to be passed in x1 and x2
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function %f13(i64, i128) -> i64 apple_aarch64 {
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block0(v0: i64, v1: i128):
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v2, v3 = isplit v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov x0, x1
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f13_call(i64) -> i64 apple_aarch64 {
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fn0 = %f13(i64, i128) -> i64 apple_aarch64
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block0(v0: i64):
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v1 = iconst.i64 42
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v2 = iconcat v0, v1
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v3 = call fn0(v1, v2)
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return v3
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: movz x2, #42
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; nextln: mov x1, x0
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; nextln: movz x0, #42
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; nextln: ldr x3, 8 ; b 12 ; data
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; nextln: blr x3
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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; We only have 8 registers to pass data in
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; make sure we spill the last argument even though there is one slot available
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function %f14(i128, i128, i128, i64, i128) -> i128 {
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block0(v0: i128, v1: i128, v2: i128, v3: i64, v4: i128):
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return v4
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: ldur x0, [fp, #16]
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; nextln: ldur x1, [fp, #24]
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f14_call(i128, i64) -> i128 {
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fn0 = %f14(i128, i128, i128, i64, i128) -> i128
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block0(v0: i128, v1: i64):
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v2 = call fn0(v0, v0, v0, v1, v0)
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; TODO: Some codegen optimization possible here with x0,x1 moving to x7,x8 and then moving back
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; nextln: mov x7, x0
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; nextln: mov x8, x1
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; nextln: mov x6, x2
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; nextln: sub sp, sp, #16
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; nextln: virtual_sp_offset_adjust 16
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; nextln: mov x0, x7
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; nextln: mov x1, x8
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; nextln: mov x2, x7
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; nextln: mov x3, x8
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; nextln: mov x4, x7
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; nextln: mov x5, x8
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; nextln: stur x7, [sp]
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; nextln: stur x8, [sp, #8]
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; nextln: ldr x7, 8 ; b 12 ; data
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; nextln: blr x7
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; nextln: add sp, sp, #16
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; nextln: virtual_sp_offset_adjust -16
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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; We have one register slot available (Similar to %f14), however apple
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; allows us to start i128 on non even numbered registers (x7 in this case).
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;
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; It is unspecified if we can split the i128 into x7 + the stack.
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; In practice LLVM does not do this, so we are going to go with that.
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function %f15(i128, i128, i128, i64, i128) -> i128 apple_aarch64{
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block0(v0: i128, v1: i128, v2: i128, v3: i64, v4: i128):
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return v4
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: ldur x0, [fp, #16]
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; nextln: ldur x1, [fp, #24]
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f15_call(i128, i64) -> i128 apple_aarch64 {
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fn0 = %f15(i128, i128, i128, i64, i128) -> i128 apple_aarch64
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block0(v0: i128, v1: i64):
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v2 = call fn0(v0, v0, v0, v1, v0)
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov x7, x0
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; nextln: mov x8, x1
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; nextln: mov x6, x2
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; nextln: sub sp, sp, #16
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; nextln: virtual_sp_offset_adjust 16
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; nextln: mov x0, x7
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; nextln: mov x1, x8
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; nextln: mov x2, x7
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; nextln: mov x3, x8
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; nextln: mov x4, x7
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; nextln: mov x5, x8
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; nextln: stur x7, [sp]
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; nextln: stur x8, [sp, #8]
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; nextln: ldr x7, 8 ; b 12 ; data
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; nextln: blr x7
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; nextln: add sp, sp, #16
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; nextln: virtual_sp_offset_adjust -16
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f16() -> i32, i32 wasmtime_system_v {
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block0:
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v0 = iconst.i32 0
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v1 = iconst.i32 1
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return v0, v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov x1, x0
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; nextln: movz x0, #0
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; nextln: movz x2, #1
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; nextln: stur w2, [x1]
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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