2986f6b0ff
* ABI: implement register arguments with constraints. Currently, Cranelift's ABI code emits a sequence of moves from physical registers into vregs at the top of the function body, one for every register-carried argument. For a number of reasons, we want to move to operand constraints instead, and remove the use of explicitly-named "pinned vregs"; this allows for better regalloc in theory, as it removes the need to "reverse-engineer" the sequence of moves. This PR alters the ABI code so that it generates a single "args" pseudo-instruction as the first instruction in the function body. This pseudo-inst defs all register arguments, and constrains them to the appropriate registers at the def-point. Subsequently the regalloc can move them wherever it needs to. Some care was taken not to have this pseudo-inst show up in post-regalloc disassemblies, but the change did cause a general regalloc "shift" in many tests, so the precise-output updates are a bit noisy. Sorry about that! A subsequent PR will handle the other half of the ABI code, namely, the callsite case, with a similar preg-to-constraint conversion. * Update based on review feedback. * Review feedback.
146 lines
2.6 KiB
Plaintext
146 lines
2.6 KiB
Plaintext
test compile precise-output
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target x86_64
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function %add_from_mem_u32_1(i64, i32) -> i32 {
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block0(v0: i64, v1: i32):
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v2 = load.i32 v0
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v3 = iadd.i32 v2, v1
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return v3
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}
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; addl %esi, 0(%rdi), %esi
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; movq %rsi, %rax
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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function %add_from_mem_u32_2(i64, i32) -> i32 {
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block0(v0: i64, v1: i32):
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v2 = load.i32 v0
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v3 = iadd.i32 v1, v2
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return v3
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}
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; addl %esi, 0(%rdi), %esi
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; movq %rsi, %rax
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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function %add_from_mem_u64_1(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = load.i64 v0
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v3 = iadd.i64 v2, v1
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return v3
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}
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; addq %rsi, 0(%rdi), %rsi
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; movq %rsi, %rax
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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function %add_from_mem_u64_2(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = load.i64 v0
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v3 = iadd.i64 v1, v2
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return v3
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}
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;; test narrow loads: 8-bit load should not merge because the `addl` is 32 bits
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;; and would load 32 bits from memory, which may go beyond the end of the heap.
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; addq %rsi, 0(%rdi), %rsi
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; movq %rsi, %rax
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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function %add_from_mem_not_narrow(i64, i8) -> i8 {
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block0(v0: i64, v1: i8):
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v2 = load.i8 v0
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v3 = iadd.i8 v2, v1
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return v3
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}
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movzbq 0(%rdi), %rax
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; addl %eax, %esi, %eax
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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function %no_merge_if_lookback_use(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = load.i64 v0
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v3 = iadd.i64 v2, v0
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store.i64 v3, v1
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v4 = load.i64 v3
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return v4
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}
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movq 0(%rdi), %r9
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; movq %r9, %r10
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; addq %r10, %rdi, %r10
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; movq %r10, 0(%rsi)
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; movq 0(%r9,%rdi,1), %rax
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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function %merge_scalar_to_vector(i64) -> i32x4 {
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block0(v0: i64):
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v1 = load.i32 v0
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v2 = scalar_to_vector.i32x4 v1
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jump block1
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block1:
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return v2
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}
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movss 0(%rdi), %xmm0
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; jmp label1
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; block1:
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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function %cmp_mem(i64) -> i64 {
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block0(v0: i64):
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v1 = load.i64 v0
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v2 = icmp eq v0, v1
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v3 = bint.i64 v2
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return v3
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}
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; cmpq 0(%rdi), %rdi
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; setz %al
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; andq %rax, $1, %rax
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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