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wasmtime/cranelift/filetests/filetests/isa/x64/vhigh_bits.clif
Trevor Elliott b077854b57 Generate SSA code from returns (#5172)
Modify return pseudo-instructions to have pairs of registers: virtual and real. This allows us to constrain the virtual registers to the real ones specified by the abi, instead of directly emitting moves to those real registers.
2022-11-08 16:00:49 -08:00

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test compile precise-output
target x86_64
function %f1(i8x16) -> i8 {
block0(v0: i8x16):
v1 = vhigh_bits.i8 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; pmovmskb %xmm0, %eax
; movq %rbp, %rsp
; popq %rbp
; ret
function %f2(i8x16) -> i16 {
block0(v0: i8x16):
v1 = vhigh_bits.i16 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; pmovmskb %xmm0, %eax
; movq %rbp, %rsp
; popq %rbp
; ret
function %f3(i16x8) -> i8 {
block0(v0: i16x8):
v1 = vhigh_bits.i8 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; movdqa %xmm0, %xmm2
; packsswb %xmm2, %xmm0, %xmm2
; pmovmskb %xmm2, %eax
; shrq $8, %rax, %rax
; movq %rbp, %rsp
; popq %rbp
; ret
function %f4(i32x4) -> i8 {
block0(v0: i32x4):
v1 = vhigh_bits.i8 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; movmskps %xmm0, %eax
; movq %rbp, %rsp
; popq %rbp
; ret
function %f5(i64x2) -> i8 {
block0(v0: i64x2):
v1 = vhigh_bits.i8 v0
return v1
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; movmskpd %xmm0, %eax
; movq %rbp, %rsp
; popq %rbp
; ret