Files
wasmtime/cranelift/filetests/filetests/isa/x64/cmp-mem-bug.clif
Trevor Elliott b077854b57 Generate SSA code from returns (#5172)
Modify return pseudo-instructions to have pairs of registers: virtual and real. This allows us to constrain the virtual registers to the real ones specified by the abi, instead of directly emitting moves to those real registers.
2022-11-08 16:00:49 -08:00

53 lines
1.1 KiB
Plaintext

test compile precise-output
target x86_64
function %f0(i64, i64) -> i64, i64 {
block0(v0: i64, v1: i64):
v2 = load.i64 v1
v3 = icmp eq v0, v2
v4 = uextend.i64 v3
v5 = select.i64 v3, v0, v1
return v4, v5
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; movq 0(%rsi), %r9
; cmpq %r9, %rdi
; setz %r10b
; movzbq %r10b, %rax
; cmpq %r9, %rdi
; movq %rsi, %rdx
; cmovzq %rdi, %rdx, %rdx
; movq %rbp, %rsp
; popq %rbp
; ret
function %f1(f64, i64) -> i64, f64 {
block0(v0: f64, v1: i64):
v2 = load.f64 v1
v3 = fcmp eq v0, v2
v4 = uextend.i64 v3
v5 = select.f64 v3, v0, v0
return v4, v5
}
; pushq %rbp
; movq %rsp, %rbp
; block0:
; movsd 0(%rdi), %xmm9
; ucomisd %xmm9, %xmm0
; setnp %dil
; setz %al
; andl %edi, %eax, %edi
; movzbq %dil, %rax
; ucomisd %xmm0, %xmm9
; movdqa %xmm0, %xmm2
; mov z, sd; j%xmm2 $next; mov%xmm0 %xmm0, %xmm0; $next:
; mov np, sd; j%xmm2 $next; mov%xmm0 %xmm0, %xmm0; $next:
; movq %rbp, %rsp
; popq %rbp
; ret